參數(shù)資料
型號: SCANPSC110FSC
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 微控制器/微處理器
英文描述: SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support)
中文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28
封裝: 0.300 INCH, MS-013, SOIC-28
文件頁數(shù): 1/25頁
文件大?。?/td> 283K
代理商: SCANPSC110FSC
2000 Fairchild Semiconductor Corporation
DS011570
www.fairchildsemi.com
March 1993
Revised August 2000
S
S
SCANPSC110F
SCAN Bridge Hierarchical and Multidrop Addressable
JTAG Port (IEEE1149.1 System Test Support)
General Description
The SCANPSC110F Bridge extends the IEEE Std. 1149.1
test bus into a multidrop test bus environment. The advan-
tage of a hierarchical approach over a single serial scan
chain is improved test throughput and the ability to remove
a board from the system and retain test access to the
remaining modules. Each SCANPSC110F Bridge supports
up to 3 local scan rings which can be accessed individually
or combined serially. Addressing is accomplished by load-
ing the instruction register with a value matching that of the
Slot inputs. Backplane and inter-board testing can easily
be accomplished by parking the local TAP Controllers in
one of the stable TAP Controller states via a Park instruc-
tion. The 32-bit TCK counter enables built in self test oper-
ations to be performed on one port while other scan chains
are simultaneously tested.
Features
I
True IEEE1149.1 hierarchical and multidrop addressable
capability
I
The 6 slot inputs support up to 59 unique addresses, a
Broadcast Address, and 4 Multi-cast Group Addresses
I
3 IEEE 1149.1-compatible configurable local scan ports
I
Mode Register allows local TAPs to be bypassed,
selected for insertion into the scan chain individually, or
serially in groups of two or three
I
32-bit TCK counter
I
16-bit LFSR Signature Compactor
I
L4
I
local TAPs can be 3-stated via the OE input to allow an
alternate test master to take control of the local TAPs
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Order Number
SCANPSC110FSC
Package Number
M28B
Package Description
28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Pin
Names
TCK
B
TMS
B
TDI
B
TDO
B
TRST
S
(0,5)
OE
TCK
L(1
3)
Local Port Test Clock Output
TMS
L(1
3)
Local Port Test Mode Select Output
TDI
L(1
3)
Local Port Test Data Input
TDO
L(1
3)
Local Port Test Data Output
Description
Backplane Test Clock Input
Backplane Test Mode Select Input
Backplane Test Data Input
Backplane Test Data Output
Asynchronous Test Reset Input (Active LOW)
Address Select Port
Local Scan Port Output Enable (Active LOW)
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