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| 型號(hào)： | OR3TP12-6BA352I |
| 英文描述： | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE |
| 中文描述： | 用戶可編程ASIC的特殊功能 |
| 文件頁(yè)數(shù)： | 93/128頁(yè) |
| 文件大?。?/td> | 2450K |
| 代理商： | OR3TP12-6BA352I |
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Lucent Technologies Inc.
Lucent Technologies Inc.
93
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
Timing Characteristics
Description
The most accurate timing characteristics are reported
by the timing analyzer in the ORCA Foundry Develop-
ment System. A timing report provided by the develop-
ment system after layout divides path delays into logic
and routing delays. The timing analyzer can also pro-
vide logic delays prior to layout. While this allows rout-
ing budget estimates, there is wide variance in routing
delays associated with different layouts.
The logic timing parameters noted in the Electrical
Characteristics section of this data sheet are the same
as those in the design tools. In the PFU timing, symbol
names are generally a concatenation of the PFU oper-
ating mode and the parameter type. The setup, hold,
and propagation delay parameters, defined below, are
designated in the symbol name by the SET, HLD, and
DEL characters, respectively.
The values given for the parameters are the same as
those used during production testing and speed bin-
ning of the devices. The junction temperature and sup-
ply voltage used to characterize the devices are listed
in the delay tables. Actual delays at nominal tempera-
ture and voltage for best-case processes can be much
better than the values given.
It should be noted that the junction temperature used in
the tables is generally 85 °C. The junction temperature
for the FPGA depends on the power dissipated by the
device, the package thermal characteristics (
Θ
JA
), and
the ambient temperature, as calculated in the following
equation and as discussed further in the Package
Thermal Characteristics section:
T
Jmax =
T
Amax
+ (P
Θ
JA
) °C
Note
: The user must determine this junction tempera-
ture to see if the delays from ORCA Foundry
should be derated based on the following derat-
ing tables.
Table 32 and Table 33 provide approximate power sup-
ply and junction temperature derating for OR3TP12
commercial devices. The delay values in this data
sheet and reported by ORCAFoundry are shown as
1.00 in the tables. The method for determining the
maximum junction temperature is defined in the Pack-
age Thermal Characteristics section. Taken cumula-
tively, the range of parameter values for best-case vs
worst-case processing, supply voltage, and junction
temperature can approach three to one.
Table 32. Derating for Commercial Devices
(
I/O Supply V
DD
)
Note: The derating tables shown above are for a typical critical path
that contains 33% logic delay and 66% routing delay. Since the
routing delay derates at a higher rate than the logic delay, paths
with more than 66% routing delay will derate at a higher rate
than shown in the table. The approximate derating values vs
temperature are 0.26% per °C or logic delay and 0.45% per
°C for routing delay. The approximate derating values vs volt-
age are 0.13% per mV for both logic and routing delays at
25 °C.
Propagation Delay
. The time between the specified
reference points. The delays provided are the worst
case of the tphh and tpll delays for noninverting func-
tions, tplh and tphl for inverting functions, and tphz and
tplz for 3-state enable.
Setup Time
. The interval immediately preceding the
transition of a clock or latch enable signal, during which
the data must be stable to ensure it is recognized as
the intended value.
Hold Time
. The interval immediately following the tran-
sition of a clock or latch enable signal, during which the
data must be held stable to ensure it is recognized as
the intended value.
3-State Enable
. The time from when a 3-state control
signal becomes active and the output pad reaches the
high-impedance state.
T
J
(
°C
)
Power Supply Voltage
3.0 V
0.82
0.91
0.98
1.00
1.23
1.34
3.3 V
0.72
0.80
0.85
0.99
1.07
1.15
3.6 V
0.66
0.72
0.77
0.90
0.94
1.01
–40
0
25
85
100
125
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR3TP12-6PS240 | Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R |
| OR3TP12-6PS240I | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R |
| OR3TP12 | Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
| OR62 | OR62 is a 6-input OR gate with 2x drive strength |
| OR73 | 7-input OR gate with 3x drive strength. |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3TP126BAN256-DB | 制造商:Lattice Semiconductor Corporation 功能描述: |
| OR3TP12-6PS240 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC |
| OR3TP12-6PS240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC |
| OR3TP127BA256-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3TP127BA352-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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