參數(shù)資料
型號(hào)： OR3TP12-6BA352I
英文描述： Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
中文描述： 用戶可編程ASIC的特殊功能
文件頁數(shù)： 79/128頁
文件大小： 2450K
代理商： OR3TP12-6BA352I
Lucent Technologies Inc.
79
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Target Controller Detailed Description
(continued)
Table 22. Dual-Port Target Read
1. When
treqn
is deasserted high, the Target interface is idle.
2. When
taenn
is asserted low, a command/address phase is in progress.
3.
taenn
must be asserted low for command/address data to transfer and state to change.
4.
taenn
must be deasserted high and
trdataenn
must be asserted low to execute the data phase.
5. Next state = 0 if
trlastcycn
is asserted low (end of Target read data).
6. Next state = 0 if
twlastcycn
is asserted low (end of Target command/address phase).
Table 23. Quad-Port Target Read
1. When
treqn
is deasserted high, the Target interface is idle.
2. When
treqn
is asserted low, a command/address phase is in progress.
3.
taenn
must be asserted low for command/address data to transfer and state to change.
4.
taenn
must be deasserted high and
trdataenn
must be asserted low to execute the data phase.
5. Next state = 0 if
trlastcycn
is asserted low (end of Target read data).
6. Next state = 0 if
twlastcycn
is asserted low (end of Target command/address phase).
tstatecntr
Next State of
tstatecntr
Description
Data on Bus
datatofpgax[3:0]
datatofpga[31:0]
XXXXXXXX
16
X
2,
Burst, Dual-Address
,
PCIAddress[31:0]
X
2,
Burst, Dual-Address
,
PCIAddress[63:32]
Data on Bus
datafmfpga[31:0]
Notes
0
0
0
Idle
—
1
1 or 0
Address[31:0]
PCIData[31:0]
2, 3, 4, 5,
6
2, 3, 4, 5,
6
1
0
Address[63:32]
PCIData[63:32]
tstatecntr
Next State of
tstatecntr
0
1 or 0
Description
Data on Bus
twdata[17:0]
XX
2
, XXXX
16
Burst, Dual-Address,
PCIAddress[15:0]
Burst, Dual-Address,
PCIAddress[31:16]
Burst, Dual-Address,
PCIAddress[47:32]
Burst, Dual-Address,
PCIAddress[63:48]
Data on Bus
trdata[15:0]
—
PCIData[15:0]
Notes
0
0
Idle
1
Address[15:0]
2, 3, 4, 6
1
2 or 0
Address[31:16]
PCIData[31:16]
2, 3, 4, 5,
6
2, 3, 4, 6
2
3 or 0
Address[47:32]
PCIData[47:32]
3
0
Address[63:48]
PCIData[63:48]
2, 3, 4, 5,
6
相關(guān)PDF資料
PDF描述
OR3TP12-6PS240 Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
OR3TP12-6PS240I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
OR3TP12 Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
OR62 OR62 is a 6-input OR gate with 2x drive strength
OR73 7-input OR gate with 3x drive strength.
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR3TP126BAN256-DB 制造商:Lattice Semiconductor Corporation 功能描述:
OR3TP12-6PS240 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP12-6PS240I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP127BA256-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP127BA352-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*