參數(shù)資料
型號(hào)： OR3TP12-6BA352I
英文描述： Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
中文描述： 用戶可編程ASIC的特殊功能
文件頁數(shù)： 33/128頁
文件大?。?/td> 2450K
代理商： OR3TP12-6BA352I
Lucent Technologies Inc.
Lucent Technologies Inc.
33
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Detailed Description
(continued)
Embedded Core/FPGA FIFO Interface Operation Summary
The following sections describe the Master and Target FIFO interface operation between the PCI bus core and the
FPGA application. Table 9 is an index to the state tables and timing figures provided for each of the operational
modes (dual-port, quad-port) of the FIFO interface.
Table 9. Index to State Sequence Tables
* The FPGA interface does not participate in Target configuration operations.
Dual-Port Mode
Quad-Port Mode
Master/
Target
PCI
Access
Type
Address
Type
Single/Burst and
Delayed/
Nondelayed
PCI
Bus
Timing
Figure
5
8
11
14
15
—
16
State
Table
FPGA
Bus
Timing
Figure
3
6
9
12
*
18
State
Table
FPGA
Bus
Timing
Figure
4
7
10
13
*
19
Master
Write
Config,
Memory, I/O
Config,
Memory, I/O
Config
I/O
Single
Burst
Single
Burst
Single
13
14
Read
15
16
17
21
Target
Write
20
Single, Delayed
Single,
Nondelayed
Single
Burst
Single
Delayed
Nondelayed
Single
Single, Delayed
Burst
Burst, Delayed
Memory
17
20
23
24
25
29
26
33
30
21
*
27
22
*
28
Read
Config
I/O
22
23
Memory
31
32
相關(guān)PDF資料
PDF描述
OR3TP12-6PS240 Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
OR3TP12-6PS240I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
OR3TP12 Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
OR62 OR62 is a 6-input OR gate with 2x drive strength
OR73 7-input OR gate with 3x drive strength.
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR3TP126BAN256-DB 制造商:Lattice Semiconductor Corporation 功能描述:
OR3TP12-6PS240 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP12-6PS240I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP127BA256-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP127BA352-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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