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| 型號： | OR3TP12-6BA352I |
| 英文描述： | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE |
| 中文描述： | 用戶可編程ASIC的特殊功能 |
| 文件頁數(shù)： | 14/128頁 |
| 文件大小： | 2450K |
| 代理商： | OR3TP12-6BA352I |
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ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
14
L Lucent Technologies Inc.
0011
I/O Write
√
√
Target:
Single accesses only, with bursts disconnected
after first data phase.
Delayed_Mode (
deltrn
= 0): Terminates the initial access
with a retry, recording internally the PCI address, byte
enables, and write data for processing by the FPGA appli-
cation. Subsequent PCI accesses occurring before the
FPGA application accepts the Target write data will result in
retries. After the Target write data is received by the FPGA
application, the next I/O write access that matches the
stored parameters (PCI address, byte enables, and write
data) disconnects with data, and the Target write logic is
cleared.
Nondelayed Mode (
deltrn
= 1,
trburstpendn
= 0): Access
posts write data into the Target write FIFOs and discon-
nects with data. The FPGA application then processes the
I/O write request and transfer data from Target write FIFOs.
Master:
Single and burst operations are allowed.
Target ignores, per PCI Specification Section 3.1.1.
Target ignores, per PCI Specification Section 3.1.1.
Target
: Single and burst accesses are allowed. The amount
of data transferred will depend on either the external PCI
Master terminating the read transaction, or the Target read
FIFOs becoming empty.
Delayed_Mode (
deltrn
= 0): Terminates the initial access
with a retry, recording internally the PCI address and byte
enables for processing by the FPGA application. Subse-
quent PCI accesses occurring before the FPGA application
loads the Target read FIFO continues to result in retries.
After the Target read FIFO is loaded by the FPGA applica-
tion, the next read access that matches the stored parame-
ters begins transfer of the FPGA supplied data.
Nondelayed Mode (
deltrn
= 1,
trburstpendn
= 0):
Accepted access inserts wait-states up to the initial latency
count (16 or 32 clocks depending on the option selected in
the FPSC configuration manager). During the wait-states,
the FPGA application processes the read request and
transfer data into the Target read FIFOs. If read data is
transferred into the Target read FIFOs before the latency
count expires, this read data is transferred to the PCI bus
during initial request. If not, the PCI address, byte enables,
and Target read data are stored in the Target controller. The
next access that matches the stored address and byte
enables begins transfer of the FPGA supplied data.
Master
: Single and burst operations are allowed.
0100
0101
0110
(reserved)
(reserved)
Memory Read
—
—
√
—
—
√
Command
Code
(Binary)
Command
OR3TP12
Master
Generates
OR3TP12
Target
Accepts
Description
PCI Bus Core Detailed Description
(continued)
Table 3. PCI Bus Command Descriptions
(continued)
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| OR3TP12-6PS240 | Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R |
| OR3TP12-6PS240I | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R |
| OR3TP12 | Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3TP126BAN256-DB | 制造商:Lattice Semiconductor Corporation 功能描述: |
| OR3TP12-6PS240 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC |
| OR3TP12-6PS240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC |
| OR3TP127BA256-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3TP127BA352-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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