參數(shù)資料
型號： OR3TP12-6BA352I
英文描述： Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
中文描述： 用戶可編程ASIC的特殊功能
文件頁數(shù)： 59/128頁
文件大小： 2450K
代理商： OR3TP12-6BA352I
Lucent Technologies Inc.
Lucent Technologies Inc.
59
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Target Controller Detailed Description
(continued)
Target Write Memory, Single-Word Transaction
Figure 17 shows the timing on the PCI bus, for a Target memory write of a single word. The timing on the PCI inter-
face (Figure 17) is similar to that of a posted I/O write (Figure 16) except that, since bursts to memory space are
allowed, the signal
stopn
is not asserted.
5-7373(F)
Figure 17. Target Memory Single Write (PCI Bus, 32-Bit)
Single Target Write FIFO Interface
The FIFO interface timing is as shown in Figure 18 and Figure 19 for dual- and quad-port respectively. The inter-
face timing is similar for all Target I/O writes and Target single memory writes, since the Target FIFO interface is
uniform across all Target accesses.
The timing on the interface (Figure 18 for dual-port) shows the first indication to the FPGA application that a new
operation is pending by the assertion of Target request (
treqn
). When
treqn
is valid, the FPGA application begins
the command/address phase by asserting Target address enable (
taenn
) and accepting the command from bus
tcmd
and address from bus
datatofpga
(
x
) (with
fifo_sel
= 1). If applicable, the dual-address indication bit accom-
panies the address on
datatofpga[0]
, whereas for the single access on a 32-bit PCI bus (
pci_64bit
= 0) the burst
indication bit (
datatofpga[1]
) will be desasserted. The FPGA application continues to receive new address data
(
taenn
asserted) on every clock until
twlastcycn
is asserted, indicating the end of the command/address phase.
See command/address section for notes regarding address transfer and alignment.
The write data phase will follow, by deassertion of
taenn
, and assertion of Target write data enable (
twdataenn
).
twdataenn
can only be asserted while
tw_emptyn
is deasserted, indicating that write data is available in the write
data FIFOs. While
twdataenn
is asserted, the FPGA application will receive Target write data on bus
datatofpga
(with
fifo_sel
= 1). The FPGA application is informed that the last component of the data phase is being presented
when
twlastcycn
is asserted. Since this is a single access on a 32-bit data bus (assuming
datatofpgax[1]
= 0 dur-
ing command/address phase,
pci_64bit
= 0), the first and only data phase is the last data of the write data phase.
T0
T1
T2
T3
T4
T5
ADDRESS
DATA
MEM WR
BYTE ENABLES
clk
framen
ad
c_ben
irdyn
devseln
trdyn
stopn
相關(guān)PDF資料
PDF描述
OR3TP12-6PS240 Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
OR3TP12-6PS240I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
OR3TP12 Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
OR62 OR62 is a 6-input OR gate with 2x drive strength
OR73 7-input OR gate with 3x drive strength.
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