參數(shù)資料
型號： OR3TP12-6BA352I
英文描述： Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
中文描述： 用戶可編程ASIC的特殊功能
文件頁數(shù)： 51/128頁
文件大?。?/td> 2450K
代理商： OR3TP12-6BA352I
Lucent Technologies Inc.
Lucent Technologies Inc.
51
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Master Controller Detailed Description
(continued)
5-7369(F)
Figure 14. Master Read Burst (PCI Bus, 32-Bit)
Table 15. Dual-Port Master Read, Specified Burst Length
1. When
maenn, mrdataenn,
and
ma_fulln
are deasserted high, the Master interface is idle.
2. When
maenn
is asserted low, a command/address phase is in progress.
3.
maenn
must be asserted low for command/address data to transfer and state to change.
4.
maenn
must be deasserted high and
mrdataenn
must be asserted low to execute the data phase.
5. Next state = 0 if
mrlastcycn
is asserted low (end of Master read data phase).
6. Next state = 0 if
mwlastcycn
is asserted low (end of Master command/address phase).
MStateCntr
Next State of
MStateCntr
Description
Data on Bus
datafmfpgax[3:0]
datafmfpga[31:0]
X
4
XXXXXXXX
16
Data on Bus
datatofpga[31:0]
Notes
0
0
Idle,
or Data[15:0]
Burst Length,
Command Word,
or Data[63:32]
Address[31:0]
Address[63:32]
PCIData[31:0]
1, 4, 5
0
1 or 0
Burst Length,
Command Word
PCIData[63:32]
2, 3, 4, 5,
6
1
2
0 or 2
0
X
4
, PCIAddress[31:0]
X
4
, PCIAddress[63:32]
—
—
2, 3, 6
2, 3, 6
T0
T1
T2
T3
T4
T5
T6
T7
T8
ADRS
D0
D1
D2
D3
CMD
BE0
BE1
BE2
BE3
clk
framen
ad
c_ben
irdyn
devseln
trdyn
stopn
相關(guān)PDF資料
PDF描述
OR3TP12-6PS240 Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
OR3TP12-6PS240I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
OR3TP12 Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
OR62 OR62 is a 6-input OR gate with 2x drive strength
OR73 7-input OR gate with 3x drive strength.
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