參數(shù)資料
型號(hào)： OR3TP12-6BA352I
英文描述： Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
中文描述： 用戶可編程ASIC的特殊功能
文件頁數(shù)： 90/128頁
文件大?。?/td> 2450K
代理商： OR3TP12-6BA352I
ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
90
L Lucent Technologies Inc.
FPGA Configuration Target Controller
Data Format
(continued)
The length and number of data frames and information
on the PROM size for the OR3TP12 is given in
Table 27.
Table 27. Configuration Frame Size
Bit Stream Error Checking
There are three different types of bit stream error
checking performed in the ORCA Series 3+ FPSCs:
ID frame, frame alignment, and CRC checking.
The ID data frame is sent to a dedicated location in the
FPSC. This ID frame contains a unique code for the
device for which it was generated. This device code is
compared to the internal code of the FPSC. Any differ-
ences are flagged as an ID error. This frame is auto-
matically created by the bit stream generation program
in ORCAFoundry.
Each data and address frame in the FPSC begins with
a frame start pair of bits and ends with eight stop bits
set to one. If any of the previous stop bits were a 0
when a frame start pair is encountered, it is flagged as
a frame alignment error.
Error checking is also done on the FPSC for each
frame by means of a checksum byte. If an error is found
on evaluation of the checksum byte, then a checksum/
parity error is flagged.
When any of the three possible errors occur, the FPSC
is forced into an idle state, forcing INIT low. The FPSC
will remain in this state until either the
RESET
or
PRGM
pins are asserted.
If using either of the
MPI
modes or the PCI embedded
core to configure the FPSC, the specific type of bit
stream error is written to one of the
MPI
registers or a
PCI register, respectively, by the FPGA configuration
logic. The
PGRM
bit of the
MPI
control register or the
PCI embedded core can also be used to reset out of
the error condition and restart configuration.
FPGA Configuration Modes
There are eight methods for configuring the FPSC. Six
of the configuration modes are selected on the M0, M1,
and M2 input and are shown in Table 28. The seventh
mode is PCI bus configuration as previously discussed,
and the eighth configuration mode is accessed through
the boundary-scan interface. A fourth input, M3, is
used to select the frequency of the internal oscillator,
which is the source for CCLK in some configuration
modes. The nominal frequencies of the internal oscilla-
tor are 1.25 MHz and 10 MHz. The 1.25 MHz fre-
quency is selected when the M3 input is unconnected
or driven to a high state.
Note that the Master parallel mode of configuration that
is available in the ORCASeries 3 FPGAs is not avail-
able in the OR3TP12. This is due to the use of Master
parallel configuration pins for the PCI bus interface.
More information on the general FPGA modes of con-
figuration can be found in the ORCA Series 3 data
sheet.
Table 28. Configuration Modes
* Motorolais a registered trademark of Motorola, Inc.
Intelis a registered trademark of Intel Corporation.
Devices
OR3TP12
Number of Frames
1240
Data Bits/Frame
232
Configuration Data (Number of frames
×
number of data bits/frame)
287,680
Maximum Total Number Bits/Frame
(align bits, 01 frame start, 8-bit check-
sum, eight stop bits)
256
Maximum Configuration Data
(number bits/frame
×
number of
frames)
317,440
Maximum PROM Size (bits)
(add configuration header and
postamble)
317,608
M2 M1 M0
CCLK
Configuration
Mode
Master Serial
Slave Parallel
Microprocessor:
Motorola* PowerPC
Microprocessor:
Intel
i960
Reserved
Async Peripheral
Reserved
Slave Serial
Data
0
0
0
0
0
1
0
1
0
Output
Input
Output
Serial
Parallel
Parallel
0
1
1
Output
Parallel
1
1
1
1
0
0
1
1
0
1
0
1
Output
Parallel
Input
Serial
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OR3TP12 Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
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