參數(shù)資料
型號: MT90866AG2
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA344
封裝: 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-344
文件頁數(shù): 75/86頁
文件大小: 701K
代理商: MT90866AG2
MT90866
Data Sheet
75
Zarlink Semiconductor Inc.
Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
Note 1:
No jitter presented on input reference clock.
Figure 35 - Local Clock Timing Diagram when ST_CKo frequency = 16.384 MHz
Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics
- Local Frame Pulse and Clock Timing,
ST_CKo = 16.384MHz
Characteristic
Sym.
Min.
Typ.
Max.
Units
Notes
1
Local Frame Boundary Offset
1
t
LFBOS
17+
ns
C
L
=30pF
2
ST_FPo0/1 Width
t
FPw16
t
FODF16
61-
61
61+
ns
3
ST_FPo0/1 Output Delay from Falling edge
of ST_FPo0/1 to falling edge of ST_CKo0/1
30.5-
/2
30.5+
/2
ns
4
ST_FPo Output Delay from Falling edge of
ST_CKo0/1 to rising edge of ST_FPo0/1
t
FODR16
30.5-
/2
30.5+
/2
ns
5
ST_CKo0/1 Clock Period
t
CP16
t
Ch16
t
CL16
61-
61
61+
ns
6
ST_CKo0/1 Clock Pulse Width High
30.5-
/2
30.5+
/2
ns
7
ST_CKo0/1 Clock Pulse Width Low
30.5-
/2
30.5+
/2
ns
8
ST_CKo0/1 Clock Rise/Fall Time
t
rC16o,
t
fC16o
14
ns
AC Electrical Characteristics
- C1M5o Output Clock Timing
Characteristic
Sym.
Min.
Typ.
Max.
Units
Notes
1
2
3
4
5
C1M5o Period
C1M5o High Time
C1M5o Low Time
C1M5o Rise Time
C1M5o Fall Time
t
C1M5oP
t
C1M5oH
t
C1M5oL
t
rC1M5o
t
fC1M5o
648-
324-
/2
324-
/2
648
324
324
648+
324+
/2
324+
/2
10
11
ns
ns
ns
ns
ns
C
L
=30 pF
t
LFBOS
Backplane Frame Boundary
t
FODR16
t
FODF16
t
CL16
t
CH16
t
FPW16
t
CP16
t
rC16o
t
fC16o
ST_FPo0/1
ST_CKo0/1
(16.384 MHz)
Local Output Frame Boundary
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