參數(shù)資料
型號(hào): MT90866AG2
廠(chǎng)商: ZARLINK SEMICONDUCTOR INC
元件分類(lèi): 路由/交換
英文描述: Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA344
封裝: 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-344
文件頁(yè)數(shù): 17/86頁(yè)
文件大?。?/td> 701K
代理商: MT90866AG2
MT90866
Data Sheet
17
Zarlink Semiconductor Inc.
1.0 Device Overview
The MT90866 can switch up to 4,096
×
2,432 channels while providing a rate conversion capability. It is designed to
switch 64 kb/s PCM or N X 64 kb/s data between the backplane and local switching applications. The device
maintains frame integrity in data applications and minimum throughput delay for voice application on a per channel
basis.
The backplane interface can operate at 8.192 Mb/s in CT-Bus mode or 16.384 Mb/s in ST-BUS mode and is
arranged in 125
μ
s wide frames that contain 128 or 256 channels respectively. A built-in rate conversion circuit
allows users to interface between backplane and local interfaces which operates at 2.048 Mb/s, 4.096 Mb/s or
8.192 Mb/s. When the device is in the local sub-rate switching mode, 2-bit 16 kb/s or 4-bit 32 kb/s data channels
can be switched within the device. The local sub-rate switching mode is available in 2 Mb/s mode only.
By using Zarlink’s message mode capability, the microprocessor can access input and output time slots on a per
channel basis. This feature is useful for transferring control and status information for external circuits or other TDM
devices.
2.0 Functional Description
A Functional Block Diagram of the MT90866 is shown in Figure 1, "Functional Block Diagram" on page 2. It is
designed to interface CT-Bus and ST-BUS serial streams from a backplane source and ST-BUS serial streams from
a local source.
3.0 Frame Alignment Timing
In the ST-BUS or the CT-Bus mode, the C8_A_io or C8_B_io pin accepts an 8.192MHz clock for the frame pulse
alignment. The FRAME_A_io or FRAME_B_io is the frame pulse signal which goes low at the frame boundary for
122 ns. The frame boundary is defined by the rising edge of the C8_A_io or C8_B_io clock during the low cycle of
the frame pulse. Figure 3, "CT-Bus Timing for 8 Mb/s Backplane Data Streams" on page 17 is the CT-Bus timing for
the backplane 8.192 Mb/s data streams and Figure 4, "ST-Bus Timing for 16 Mb/s Backplane Data Streams" on
page 18 is the ST-BUS timing for the 16.384 Mb/s backplane data stream.
Figure 3 - CT-Bus Timing for 8 Mb/s Backplane Data Streams
FRAME_A_io,
FRAME_B_io
C8_A_io,
C8_B_io
(8.192MHz)
(CT Frame)
7
2
3
4
5
6
1
0
0
STio 0 - 31
(8Mb/s mode)
1
2
3
4
5
6
1
0
7
Channel 127
Channel 0
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