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參數(shù)資料
| 型號： | MT90866AG2 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PBGA344 |
| 封裝： | 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-344 |
| 文件頁數(shù)： | 41/86頁 |
| 文件大?。?/td> | 701K |
| 代理商： | MT90866AG2 |
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MT90866
Data Sheet
41
Zarlink Semiconductor Inc.
The frequency stability of the Holdover Mode is
±
0.07 ppm, which translates to a worst case 49 frame (125
μ
s) slips
in 24 hours.
Two factors affect the frequency stability of the Holdover Mode. The first factor is the drift on the frequency of the
master clock (C20i) while in the Holdover Mode. Drift on the master clock directly affects the Holdover Mode
stability. Note that the absolute master clock stability does not affect the Holdover Frequency stability, only the
change in C20i stability while in Holdover. For example, a
±
32 ppm master clock may have a temperature
coefficient of
±
0.1 ppm/
°
C. So a 10 degree change in temperature, while the DPLL is in the Holdover Mode may
result in an additional offset (over the
±
0.07 ppm) in frequency stability of
±
1 ppm, which is much greater than the
±
0.07 ppm of the DPLL. The second factor affecting Holdover frequency stability is large jitter on the reference input
prior to the mode switch.
18.10.3 Freerun Mode
When the DPLL is in the Holdover Mode and the HRST bit of the DOM2 register is pulsed logic high (or held high
continuously), the device is in Freerun Mode.
In Freerun Mode, the DPLL provides timing and synchronization signals which are based on the frequency of the
master clock (C20i) only, and are not synchronized to the reference input signals. The frequency of the output
signals is an ideal frequency with the freerun accuracy of -0.03 ppm plus the accuracy of the master clock (i.e.,
CT_C8 has frequency of 8.192 MHz +/- C20i_accuracy - 0.03 ppm).
Freerun Mode is typically used when a master clock source is required, or immediately following system power-up
before network synchronization is achieved.
19.0 Measures of Performance
The following are some the DPLL performance indicators and their corresponding definitions.
19.1 Intrinsic Output Jitter
Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output. It is measured by
applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Intrinsic jitter may
also be measured when the device is in a non-synchronizing mode, such as freerun or holdover, by measuring the
output jitter of the device. Intrinsic jitter is usually measured with various band-limiting filters depending on the
applicable standards.
19.2 Jitter Tolerance
Jitter tolerance is a measure of the ability of a PLL to operate properly without cycle slips (i.e., remain in lock and
regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its
reference. The applied jitter magnitude and the jitter frequency depends on the applicable standards. The input jitter
tolerance of the DPLL depends on the selected reference frequency and can not exceed:
± 15
U.I. for E1
or T1
references, and ± 1 U.I. for 8 kHz references.
19.3 Jitter Transfer
Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter
at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured
with various filters depending on the applicable standards.
In slave and secondary master mode the H.110 standard requires the “B Clocks” to be edge-synchronous with the
“A Clocks”, as long as jitter on the “A Clocks” meets Telcordia GR-1244-CORE specifications. Therefore in these
two modes no jitter attenuation is performed
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相關代理商/技術參數(shù) |
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|---|---|
| MT90866AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:WAN Access Switch |
| MT90868AG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 32KX8K/8KX8K/1K X 1K 1.8V/3.3V 466BGA - Trays |
| MT90868AG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 32KX8K/8KX8K/1K X 1K 1.8V/3.3V 466BGA - Trays |
| MT90869 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 16K Digital Switch (F16kDX) |
| MT90869AG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 16KX16K/8KX8K 1.8V/3.3V 272BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F16KDX 272PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F16KDX 272PBGA |
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