參數(shù)資料
型號: MT90866AG2
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA344
封裝: 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-344
文件頁數(shù): 13/86頁
文件大?。?/td> 701K
代理商: MT90866AG2
MT90866
Data Sheet
13
Zarlink Semiconductor Inc.
K18, K19, K20,
L20, L18, L19,
M18, M19, M20,
N20, N19, N18
STo16 - 27
Serial Output Streams 16 to 27 (5 V Tolerant Tri-state Outputs).
In 2Mb/s
mode, these outputs have data rate of 2.048 Mb/s with 32 channels per
stream. In 4 Mb/s or 8 Mb/s mode, the STo16 - 18 outputs have data rates of
4.096 Mb/s or 8.192 Mb/s with 64 or 128 channels per stream respectively;
STo19 - 27 are driven low. No sub-rate switching mode is offered for
STo16-27.
R18
ODE
Output Drive Enable (5 V Tolerant Input).
When this pin is low, STo0 to
STo27, STio0 to STio31, C1M5o, C32/64o, ST_CKo0, ST_CKo1, ST_FPo0
and ST_FPo1 outputs are all in high-impedance state. When ODE is high all
of the aforementioned pins are active.
J2
BCSTo
Backplane Control Signal (Output)
. This pin is used for backplane
external tristate controllers. When this signal is high, the corresponding
output channels are in a high impedance state. BCSTo’s bit rate is
32.768 MHz.
E18
LCSTo
Local Control Signal (Output).
This pin is used for local external tristate
control. When this signal is high, the corresponding ouput channels are in a
high impedance state. The bit rate is 32.768 MHz.
Y13
C20i
Master Clock (5 V Tolerant Input).
This pin accepts a 20.000 MHz clock.
R19
C8_A_io
Clock A (5 V Tolerant I/O).
This is a 8.192 MHz clock with 50% duty cycle.
R20
FRAME_A_io
Frame Reference A (5 V Tolerant I/O).
This is a 122 ns wide, negative
pulse, with 125 us period.
P20
A_Active
A Clock Active Indicator (5 V Tolerant Output):
This pin indicates whether
the C8_A_io and the FRAME_A_io pins are inputs or outputs. When Bit 13
of the DOM1 register is low, this pin drives low and the C8_A_io and
FRAME_A_io output drivers are disabled. When Bit 13 of the DOM1 register
is high, this pin drives high and the C8_A_io and FRAME_A_io output
drivers are enabled.
T19
C8_B_io
Clock B (5 V Tolerant I/O).
This is a 8.192 MHz clock with 50% duty cycle.
T18
FRAME_B_io
Frame Reference B (5 V Tolerant I/O).
This is a 122 ns wide, negative
pulse, with 125 us period.
P19
B_Active
B Clock Active Indicator (5 V Tolerant Output):
This pin indicates whether
the C8_B_io and the FRAME_B_io pins are inputs or outputs. When Bit 14
of the DOM1 register is low, this pin drives low and the C8_B_io and
FRAME_B_io output drivers are disabled. When Bit 14 of the DOM1 register
is high, this pins drives high and the C8_B_io and FRAME_B_io output
drivers are enabled.
T20
FAIL_A
A Failure (Output).
When the C8_A_io or the FRAME_A_io signal fails, this
signal goes to high.
U18
FAIL_B
B Failure (Output).
When the C8_B_io or the FRAME_B_io signal fails, this
signal goes to high.
U19
CTREF1
CT-Bus Reference 1 (5 V Tolerant Input).
This pin accepts 8KHz,
1.544 MHz or 2.048 MHz network timing reference.
Pin Description (continued)
PBGA
Ball Number
Name
Description
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