參數(shù)資料
型號: MT90866AG2
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA344
封裝: 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-344
文件頁數(shù): 61/86頁
文件大?。?/td> 701K
代理商: MT90866AG2
MT90866
Data Sheet
61
Zarlink Semiconductor Inc.
Bit
15 - 9
Name
Description
POS6 - POS0
Phase Offset Bits:
These seven bits refer to the 2’s complement phase word to
control the DPLL output phase offset. The offset varies in steps of 15 ns if the
reference is 8 kHz or 2.048 MHz. The offset varies in steps of 20 ns if the reference
is 1.544 MHz.
Reserved.
Skew Control Bits:
These three bits control the delay of the DPLL outputs from 0
to 7 steps in interval of maximum unit delay of 3.5 ns.
8 - 3
2 - 0
Unused
SKC2 - SKC0
Table 23 - DPLL Output Adjustment (DPOA) Register Bits
Bit
15 - 7
6
Name
Unused
SLS
Description
Reserved.
Secondary Loss Detection Bit (Read-only bit):
This bit is the same as the output
from the DPLL Reference Monitor FAIL_SEC.
Primary Loss Detection Bit (Read-only bit):
This bit is the same as the output from
the DPLL Reference Monitor FAIL_PRI.
DPLL Clock Monitor Bit:
When high, the primary output C32/64o is 65.536 MHz clock.
When low, the primary output C32/64o is 32.768 MHz clock. This is the only writable bit
in this register.
Limit (Read-only bit):
Indicates that DPLL Phase Slope limiter limits input phase.
5
PLS
4
CKM
3
Limit
Table 24 - DPLL House Keeping (DHKR) Register Bits
Read/Write Address: 002D
H
for DPOA Register
Reset Value: 0000
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
POS
6
POS
5
POS
4
POS
3
POS
2
POS
1
POS
0
0
0
0
0
0
0
SKC2
SKC1
SKC0
Read/Write Address: 002E
H
for DHKR Register
Reset Value: 0000
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
SLS
PLS
CKM
Limit
State 2
State 1
State 0
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