參數(shù)資料
型號(hào)： MT90866AG2
廠商： ZARLINK SEMICONDUCTOR INC
元件分類(lèi)： 路由/交換
英文描述： Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch
中文描述： TELECOM, DIGITAL TIME SWITCH, PBGA344
封裝： 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-344
文件頁(yè)數(shù)： 14/86頁(yè)
文件大小： 701K
代理商： MT90866AG2
MT90866
Data Sheet
14
Zarlink Semiconductor Inc.
U20
CTREF2
CT-Bus Reference 2 (5 V Tolerant Input).
This pin accepts 8KHz,
1.544 MHz or 2.048 MHz network timing reference.
W17, Y17, V16,
W16, Y16, V15,
W15, Y15
LREF0- 7
Local Reference (
5 V Tolerant
Inputs).
These pins accept 8 KHz,
1.544 MHz or 2.048 MHz local timing reference.
V17
NREFo
Network Reference Output (Output).
Any local reference can be switched
to this output. The output data rate can be either the same as the selected
reference input data rate or divided to be 8 KHz.
Y20
PRI_LOS
Primary Reference Lost (5 V Tolerant Input).
When this signal is high, it
indicates that PRIMARY REFERENCE is not valid. Combined with
SEC_LOS input, this input pin is used in the External Reference Switching
Mode of the DPLL.
Y19
SEC_LOS
Secondary Reference Lost (5 V Tolerant Input).
When this signal is high,
it indicates that SECONDARY REFERENCE is not valid. Combined with the
PRI_LOS input, this input pin is used in the External Reference Switching
Mode of the DPLL.
W14
FAIL_PRI
Primary Reference Failure (5 V Tolerant Output)
. This pin reflects the
logic status of the PLS bit of the DPLL House Keeping Register (DHKR).
When the primary reference fails, this signal goes to 1.
Y14
FAIL_SEC
Secondary Reference Failure (5 V Tolerant Output)
.
This pin reflects the
logic status of the SLS bit of the DPLL House Keeping Register (DHKR).
When the secondary reference fails, this signal goes to 1.
W18
C32/64o
C32/64o Clock (5 V Tolerant Output).
A 32.768 MHz output clock when the
DPLL Clock Monitor register bit (CKM) is low. A 65.536 MHz clock when the
DPLL Clock Monitor register bit (CKM) is high.
Y18
C1M5o
C1.5o Clock (5 V Tolerant Output).
A 1.544 MHz output clock.
V20
ST_FPo0
ST-Bus Frame Pulse Output (5 V Tolerant Output).
The width of this
output ST-Bus frame pulse can be 244 ns, 122 ns or 61 ns. The frequency is
8 KHz.
V19
ST_CKo0
ST-Bus Clock Output (5 V Tolerant Output).
The frequency of this output
ST-Bus clock can be 4.096 MHz, 8.192 MHz or 16.384 MHz.
W8
ST_FPo1
ST-Bus Frame Pulse Output (5 V Tolerant Output)
. The width of this
output ST-Bus frame pulse can be 244 ns, 122 ns or 61 ns. The frequency is
8 KHz.
Y8
ST_CKo1
ST-Bus Clock Output (5 V Tolerant Output)
. The frequency of this output
ST-Bus clock can be 4.096 MHz, 8.192 MHz or 16.384 MHz.
V1
CS
Chip Select (5 V Tolerant Input).
This active low input is used by the
microprocessor to access the microport.
W1
DS
Data Strobe (5 V Tolerant Input).
This active low input works in conjunction
with CS to initiate the read and write cycles.
Y1
R/W
Read/Write (5 V Tolerant Input).
This input controls the direction of the data
bus lines (D0 - D15) during the microprocessor access.
Pin Description (continued)
PBGA
Ball Number
Name
Description
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