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參數(shù)資料
| 型號： | MT90866AG2 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PBGA344 |
| 封裝： | 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-344 |
| 文件頁數(shù)： | 32/86頁 |
| 文件大?。?/td> | 701K |
| 代理商： | MT90866AG2 |
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MT90866
Data Sheet
32
Zarlink Semiconductor Inc.
16.0 DPLL
The Digital Phase Locked Loop (DPLL) accepts selectable 1.544 MHz, 2.048 MHz, or 8 kHz input reference
signals. It accepts reference inputs from independent sources and provides bit-error-free reference switching. The
DPLL meets phase slope and MTIE requirements defined by the Telcordia GR-1244-CORE standard.
The DPLL also provides the timing for the rest of the MT90866 Digital Switch, generating several network clocks
with the appropriate quality. Clocks are synchronized to one of two input reference clocks and meet the
requirements of the H.110 clock specification.
The master clock (CLK80M) for the DPLL is provided by the Analog Phase Locked Loop (APLL) from the MT90866
master clock input pin C20i. Since the APLL output is “l(fā)ocked” to the input, the accuracy of CLK80M clock is equal
to the accuracy of C20i.
16.1 MT90866 Modes of Operation
The DPLL, and consequently the MT90866, can, as required by the H.110 standard, operate in three different
modes: Primary Master, Secondary Master and Slave. See Figure 12, "Typical Timing Control Configuration" on
page 32.
To configure the DPLL, there are two Operation Mode registers: DOM1 and DOM2. See Table 20 on page 55 and
Table 21, "DPLL Operation Mode (DOM2) Register Bits" on page 58 for the contents of these registers.
In all modes the MT90866 monitors both the “A Clocks” (C8_A_io and FRAME_A_io) and the “B Clocks” (C8_B_io
and FRAME_B_io). The Fail_A and the Fail_B signals indicate the quality of the “A Clocks” and “B Clocks”
respectively.
Figure 12 - Typical Timing Control Configuration
16.1.1 Primary Master Mode
In the Primary Master Mode, the MT90866 drives the “A Clocks” (C8_A_io and FRAME_A_io), by locking to the
primary reference (PRI_REF). The PRI_REF can be provided by one of the locally derived network reference
sources (LREF0-7), or the CTREF1 input or the CTREF2 input. In this mode the MT90866 has the ability to monitor
the primary reference. If the primary reference becomes unreliable, the device continues driving “A Clocks” in
stable Holdover Mode until it makes a
Stratum 4 Enhanced
compatible switch to the secondary reference
(SEC_REF) for its network timing. The secondary reference can be provided by one of the local network references
(LREF0-7), the CTREF1 or the CTREF2.
CT_C8_A/CT_FRAME_A
CT_NETREF1
CT_NETREF2
A
Network Ref
(8kHz / T1 / E1)
PRIMARY
MASTER
CT_C8_B/CT_FRAME_B
B
C
LREF0-7
C
A
B
C
LREF0-7
C
SECONDARY
MASTER
SLAVE
A
B
LREF0-7
N
SLAVE
A
B
LREF0-7
N
Network Ref
(8kHz / T1 / E1)
Network Ref
(8kHz / T1 / E1)
Network Ref
(8kHz / T1 / E1)
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT90866AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:WAN Access Switch |
| MT90868AG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 32KX8K/8KX8K/1K X 1K 1.8V/3.3V 466BGA - Trays |
| MT90868AG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 32KX8K/8KX8K/1K X 1K 1.8V/3.3V 466BGA - Trays |
| MT90869 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 16K Digital Switch (F16kDX) |
| MT90869AG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 16KX16K/8KX8K 1.8V/3.3V 272BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F16KDX 272PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F16KDX 272PBGA |
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