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參數(shù)資料
| 型號： | MT90866AG2 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PBGA344 |
| 封裝： | 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-344 |
| 文件頁數(shù)： | 39/86頁 |
| 文件大?。?/td> | 701K |
| 代理商： | MT90866AG2 |
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MT90866
Data Sheet
39
Zarlink Semiconductor Inc.
18.5 Phase Slope Limiter
The limiter receives the error signal from the Phase Offset Adder circuit and ensures that the DPLL responds to all
input transient conditions with a maximum output phase slope of 7.6 ns per 125 us. Because of this slope, the
MT90866 is within the maximum phase slope of 81 ns per 1.326 ms specified by the Telcordia GR-1244-CORE
standard.
The frequency stability of the Holdover Mode is
±
0.07 ppm, which translates to a worst case 49 frame (125
μ
s) slips
in 24 hours. This is better than the Telcordia GR-1244-CORE Stratum 3 requirement of
±
0.37 ppm (255 frame slips
per 24 hours).
18.6 Loop Filter
The Loop Filter circuit gives frequency offset to the DCO circuit, based on the phase difference between the input
and the feedback reference. It is similar to a first order low pass filter, with two positions for cut-off frequency (-3 dB
attenuation) depending on the selected reference frequency, and it mainly determines the jitter transfer function of
the DPLL.
In Primary Master mode when the selected input reference frequency is either 2.048 MHz, 1.544 MHz or 8 kHz, the
cut-off frequency is approximately at 1.52 Hz and all the reference variations, including jitter, are attenuated
according to the DPLL jitter transfer function (see Figure 17, "DPLL Jitter Transfer Function Diagram - wide range of
frequencies" on page 42 and Figure 18, "Detailed DPLL Jitter Transfer Function Diagram" on page 43). The Loop
Filter circuit ensures that the jitter transfer requirements in ETS 300-011 and Telecordia GR-499-CORE are met
when the selected reference frequency is either 2.048 MHz, 1.544 MHz or 8 kHz.
When the selected input reference frequency is 8.192 MHz (i.e., in Secondary Master or Slave modes), the
reference variations are bypassed to the output clocks. The cut-off frequency is at about 100 kHz, well beyond
500 Hz, the corner frequency of the Telcordia GR-1244-CORE input jitter tolerance curve.
The storage techniques, which enable generating very accurate output frequencies during the Holdover Mode of
DPLL, are built into the Loop Filter circuit. When no jitter is presented on the selected input reference, the holdover
frequency stability is 0.007 ppm.
18.7 Digitally Controlled Oscillator (DCO)
The DCO circuit adds frequency offset from the Loop Filter, which represents the phase error between the input and
the feedback reference, to the ideal center frequency value and generates appropriately corrected output high
speed clock. The Synchronization method of the DCO is dependent on the state of the DPLL State Machine
module.
In the Normal Mode, the DCO circuit provides an output signal which is frequency and phase locked to the selected
input reference signal.
In the Holdover Mode, the DCO circuit is running at a frequency that is equal to the frequency which was generated
by the DCO circuit when the DPLL was in the Normal Mode.
In the Freerun Mode, the DCO circuit is free running at its center frequency with an output accuracy equal to the
accuracy of the device master clock (C20i).
18.8 Divider
The Divider Circuit divides the DCO output frequency down to the required outputs. The following outputs are
generated:
C64 (65.536 MHz clock) - used as the internal clock for the MT90866 device.
CT_C8 (8.192 MHz clock), C2M (2.048 MHz clock), C1M5o (1.544 MHz clock) and CT_FRAME (8 kHz
negative frame pulse) - feedback reference signals to the Frequency Select MUX Circuit.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MT90866AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:WAN Access Switch |
| MT90868AG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 32KX8K/8KX8K/1K X 1K 1.8V/3.3V 466BGA - Trays |
| MT90868AG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 32KX8K/8KX8K/1K X 1K 1.8V/3.3V 466BGA - Trays |
| MT90869 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 16K Digital Switch (F16kDX) |
| MT90869AG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 16KX16K/8KX8K 1.8V/3.3V 272BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F16KDX 272PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F16KDX 272PBGA |
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