參數(shù)資料
型號: MT90866AG2
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA344
封裝: 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-344
文件頁數(shù): 55/86頁
文件大?。?/td> 701K
代理商: MT90866AG2
MT90866
Data Sheet
55
Zarlink Semiconductor Inc.
Bit
Name
Description
15 - 0
BBER15 -BBER0
Backplane Bit Error Rate Count Bits:
These bits refer to the backplane bit
error count. This counter stops incrementing when it reaches the value 0xFFFF.
Table 19 - Backplane Bit Error Rate Register (BBERR) Bits
Bit
Name
Description
15
CNEN
NREFo Output Enable Bit:
When CNEN is low, NREFo output is disabled, i.e. tri-stated.
When CNEN is high, NREFo output is enabled.
B Clocks Output Enable Bit:
When BEN is low, the “B Clocks” (C8_B_io and FRAME_B_io)
are disabled, i.e. tri-stated - C8_B_io and FRAME_B_io behave as inputs.
14
BEN
When BEN is high, the “B Clocks” are enabled - C8_B_io and FRAME_B_io behave as
outputs.
A Clocks Output Enable Bit:
When AEN is low, the “A Clocks” (C8_A_io and FRAME_A_io)
are disabled, i.e. tri-stated - C8_A_io and FRAME_A_io behave as inputs.
13
AEN
When AEN is high, the “A Clocks” are enabled - C8_A_io and FRAME_A_io behave as
outputs.
Reference Selection Bit:
When RPS is low, the preferred reference is the primary reference
(PRI_REF). When RPS is high, the preferred reference is the secondary reference
(SEC_REF).
11 - 10 FS1 - FS0
SEC_REF Frequency Selection Bits:
These bits are used to select different clock
frequencies for the secondary reference.
12
RPS
Table 20 - DPLL Operation Mode (DOM1) Register Bits
Read/Write Address: 002B
H
for DOM1 Register
Reset Value: 0000
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CNEN
BEN
AEN
RPS
FS1
FS0
FP1
FP0
SS3
SS2
SS1
SS0
SP3
SP2
SP1
SP0
FS1
FS0
Secondary Reference
0
0
8kHz
0
1
1.544MHz
1
0
2.048MHz
1
1
8.192MHz (“A Clocks” or “B Clocks”)
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