參數(shù)資料
型號(hào): MT90221AL
廠商: Mitel Networks Corporation
英文描述: Quad IMA/UNI PHY Device
中文描述: 四IMA的/單向物理層設(shè)備
文件頁數(shù): 73/114頁
文件大小: 304K
代理商: MT90221AL
MT90221
65
Address (Hex):
Direct access
Reset Value (Hex):
188 - 18B
1 register per IMA Group
00
Bit #
Type
Description
7
R
R
Unused. Read 0.
Reserved.
When set to 1, it enables the automatic selection of the Reference link for the Group.
When 0, the link specified in bits 1-0 is used as the reference link.
Reserved. Write 0 for normal operation.
These 2 bits specify which physical link is to be used as the reference link for the IMA
Group.
6:4
3
R/W
2
R/W
R/W
1:0
Table 78 - RX Reference Link Control Registers
Address (Hex):
Direct access
Reset Value (Hex):
18C - 18F
1 register per IMA Group
05
Bit #
Type
Description
7:4
3:0
R
Unused. Read all 0s.
Defines the integration period for an IMA Group
1111: Reserved. Do not use.
1110: 2
21
clock cycles
1101: 2
20
clock cycles
1100: 2
19
clock cycles (preferred value for E1)
1011: 2
18
clock cycles (preferred value for T1 - 24 channels)
1010: 2
17
clock cycles
1001: 2
16
clock cycles (preferred value for T1 - 23 channels)
1000: 2
15
clock cycles
0111: 2
14
clock cycles
0110: 2
13
clock cycles
0101: 2
12
clock cycles
0100: 2
11
clock cycles
0011: 2
10
clock cycles
0010: 2
09
clock cycles
0001: 2
08
clock cycles
0000: 2
07
clock cycles
R/W
Table 79 - RX IDCR Integration Registers
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