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參數(shù)資料
| 型號： | MT90221AL |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad IMA/UNI PHY Device |
| 中文描述： | 四IMA的/單向物理層設(shè)備 |
| 文件頁數(shù)： | 31/114頁 |
| 文件大小： | 304K |
| 代理商： | MT90221AL |
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MT90221
23
4.0 Description of the PCM Interface
To provide support for the IMA Asymmetrical mode,
the Transmit PCM blocks are independent from the
Receive PCM blocks. The TX port of a framer can be
connected to any of the MT90221 TX UTOPIA Input
ports and the RX port of a framer can be connected
to any of the MT90221 RX UTOPIA Output ports.
4.1
Serial to Parallel (S/P) and Parallel to Serial
(P/S) Converters
Each T1/E1 link has a S/P and P/S unit assigned.
The P/S unit takes a byte from the cell RAM and
converts it to a serial bit stream. The S/P unit takes a
byte from the DSTi input and converts it to parallel
format for use by the Cell Delineation block.
The system interface supports both the ST-BUS
(2.048 Mbps bus) and generic PCM Interface. Note
that the ST-BUS is compatible with the so-called
MVIP mode that is supported by some T1 or E1
framer manufacturers.
The MT90221 generates and receives the PCM
channels only (24 or 23 with T1, 30 with E1). The
control/status channels of the framers and the
signaling channels are
MT90221.
not supported by the
P/S and S/P units can be set-up differently on a per
port and per direction basis (i.e. the transmit and
receive function of the same port can use different
configurations).
supported:
programming links as T1 or E1
using ST-BUS and Generic PCM modes
enabling/disabling the P/S and S/P units (if they
are disabled the associated outputs are Tri-
stated)
mapping T1 links, on a per port and per
direction basis, to use either the first 24
channels or 3 of every 4 channels (when ST-
BUS or 2.048 clock modes are selected)
programming T1 links to ignore timeslot 24 and
reserve it for signaling (since only 23 timeslots
are used to carry the ATM cells, this option
should be applied to all links of the same IMA
Group)
independently programming the polarity of
RXCK, TXCK, RXSYNC and TXSYNC signals
(Generic PCM mode only)
generating/accepting TXSYNC and TXCLK
signals to support most T1 and E1 framers
(depending on the programmed mode)
monitoring RXSYNC signal period and
reporting the unexpected occurrence of a
synchronization signal (see 4.3.1 Verification of
the RXSYNC Period, for more details)
monitoring TXSYNC signal period (when
defined as input) and reporting the unexpected
occurrence of a synchronization signal (see
4.3.2 Verification of the TXSYNC Period, for
more details)
The
following
features
are
Figure 8 - Example of UNI Mode Operation
.
RXCK
RXSYNC
DSTi
S/P
RXCK
RXSYNC
DSTi
RXCK
RXSYNC
DSTi
RXCK
RXSYNC
DSTi
UTOPIA
Interface
Cell
System Clock
S/P
S/P
S/P
Delineation
Idle Cell
Removal
Cell
Delineation
Idle Cell
Removal
Cell
Delineation
Idle Cell
Removal
Cell
Delineation
Idle Cell
Removal
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT90222 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:4/8/16 Port IMA/TC PHY Device |
| MT90222AG | 制造商:Microsemi Corporation 功能描述:ATM IMA 40MBPS 2.5V 384BGA - Trays |
| MT90222AG2 | 制造商:Microsemi Corporation 功能描述:ATM IMA 40MBPS 2.5V 384BGA /BAKE/DRYPACK - Trays |
| MT90223AG | 制造商:Microsemi Corporation 功能描述:ATM IMA 80MBPS 2.5V 384BGA - Trays |
| MT90223AG2 | 制造商:Microsemi Corporation 功能描述:ATM IMA 80MBPS 2.5V 384BGA - Trays |
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