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參數資料
| 型號： | MT90221AL |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad IMA/UNI PHY Device |
| 中文描述： | 四IMA的/單向物理層設備 |
| 文件頁數： | 50/114頁 |
| 文件大小： | 304K |
| 代理商： | MT90221AL |
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MT90221
42
a. Unassigned Cells have a fixed header corresponding to 00000000 00000000 00000000 0000xxx0.
b. Idle Cells have a fixed header corresponding to 00000000 00000000 00000000 00000001
Address (Hex):
Direct access
00D
1 register to enable the IMA Groups. The TxClk signal must be active for correct
register operation
00
Reset Value (Hex):
Bit #
Type
Description
7-4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
Reserved. Write all 0’s.
Enable UTOPIA PHY address of IMA Group 3. A 1 enables the PHY port Address.
Enable UTOPIA PHY address of IMA Group 2. A 1 enables the PHY port Address.
Enable UTOPIA PHY address of IMA Group 1. A 1 enables the PHY port Address.
Enable UTOPIA PHY address of IMA Group 0. A 1 enables the PHY port Address.
Table 15 - UTOPIA Input Group PHY Enable Register
Address (Hex):
Direct access
00E
1 register for all the UTOPIA Input ports. The TxClk signal must be active for
correct register operation
00
Reset Value (Hex):
Bit #
Type
Description
7
6
R
Reserved.
UTOPIA Input Reset. A 1 will reset the UTOPIA Input State Machine. All other user
programmable registers are not cleared. A 0 is used for normal operation.
Reserved. Write 0.
Unassigned Cell Filter. A 1 signifies that the Unassigned
a
cells coming from the ATM layer
will be discarded. The Unassigned/Idle cell counter is incremented for each cell
discarded.
Idle Cell Filter. A 1 signifies that the Idle
b
cells coming from the ATM layer will be
discarded. The Unassigned/Idle cell counter is incremented for each cell discarded.
ATM Forum Polynomial. A 1 disables the addition of the ATM Forum Polynomial
calculation on the HEC calculated as per I.432. A 0 means that the closest value is
included in the HEC value.
HEC Verification.
11: Enable HEC error correction if 1 bit is wrong, discard cell if more than 1 bit are wrong.
10: Discard cell if HEC is wrong, ho HEC correction.
01: Enable HEC error correction if 1 bit is wrong, no correction if more than 1 bit wrong,
cell is not discarded if HEC is wrong.
00: No verification of HEC.
R/W
5
4
R/W
R/W
3
R/W
2
R/W
1-0
R/W
Table 16 - Utopia Input Control Register
Address (Hex):
Direct access
040 - 043
1 register per link in UNI mode. The RxClk signal must be active for correct
register operation
00
Reset Value (Hex):
Bit #
Type
Description
7:5
4:0
R
Unused. Read all 0’s.
UTOPIA PHY Address of link N when in UNI (non-IMA) mode.
R/W
Table 17 - UTOPIA Output Link Address Registers
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