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參數(shù)資料
| 型號(hào)： | MT90221AL |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad IMA/UNI PHY Device |
| 中文描述： | 四IMA的/單向物理層設(shè)備 |
| 文件頁(yè)數(shù)： | 42/114頁(yè) |
| 文件大?。?/td> | 304K |
| 代理商： | MT90221AL |
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MT90221
34
bit of the
Counter Transfer Command
register. The
value ’0x001010’ enables the counter IRQ and
’xxx00010’ disables (masks) it.
6.2
The MT90221 can generate interrupts from many
sources. All interrupt sources can be enabled or
disabled. Write action is required to clear the source
of interrupt. Interrupts are grouped on a per link
basis, with six sub-categories for each link and two
special types for the IMA Group configuration. These
special interrupts are only present in the Link 0 IRQ
Status
register.
Refer
representation of the interrupt register hierarchy.
Interrupt Block
to
Figure
18
for
a
6.2.1
IRQ Master Status and IRQ Master Enable
Registers
There is a
Master IRQ Status
register that reports
interrupts generated by any event on any of the eight
links. Each bit of this register corresponds to a link. A
’1’ in a bit position indicates that the associated link
is reporting an interrupt condition. For each bit in the
IRQ Master Status
register, there is a corresponding
bit in the
IRQ Master Enable
register. When any IRQ
source is active and the corresponding Enable bit is
’1’, then the IRQ pin will go LOW (active).
The
IRQ Master Status
register always reports the
current state of the source(s) of interrupt. It does not
latch the interrupt request(s); it only reports that one
or more bit(s) in one or more
IRQ Link Status
register(s) is (are) set.
The bits that are read as active (’1’ value) are
cleared when the source of the interrupt is cleared or
when the corresponding bit(s) in the
IRQ Link
Enable
register(s) is (are) set to 0. Writing to or
reading from the
IRQ Master Status
register has no
effect on the level of the interrupt pin.
6.2.2
Registers
There are four
IRQ Link Status
and four
IRQ Link
Enable
registers; one of each per link. The following
IRQ Link Status and IRQ Link Enable
Figure 18 - IRQ Register Hierarchy
S
T
A
T
U
S
Group Counters
UTOPIA IMA
Link 3
Link 2
Link 1
Link 0
Link 0
Link 3
IRQ PIN
LCD
LIF
LODS
IV
New RX ICP
Link UNI Overflow Status
Counters
Counters
4 TX
4 RX
S
T
A
T
U
S
Counters
4 UTOPIA
S
T
A
T
U
S
S
T
A
T
U
S
IMA
READY BIT/ICP CELL TIME *
Note
*
: These 2 IRQ signals are
only present in IRQ Status
register for Link 0.
1 UTOPIA
RX FIFO Overflow
IMA Group
OVERFLOW
1 set of registers
OVERFLOW
4 registers
Counters
4 UTOPIA
1 UTOPIA
RX FIFO Overflow
Frame
Pulse
Transfer
Done
TX ICP Cell
Handler Register
S
T
A
T
U
S
S
T
A
T
U
S
4 x IRQ
Link
Registers
1 x IRQ
Master
Registers
IMA GRP CNTRS
*
E
N
A
B
L
E
E
N
A
B
L
E
E
N
A
B
L
E
E
N
A
B
L
E
0
7
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90222 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:4/8/16 Port IMA/TC PHY Device |
| MT90222AG | 制造商:Microsemi Corporation 功能描述:ATM IMA 40MBPS 2.5V 384BGA - Trays |
| MT90222AG2 | 制造商:Microsemi Corporation 功能描述:ATM IMA 40MBPS 2.5V 384BGA /BAKE/DRYPACK - Trays |
| MT90223AG | 制造商:Microsemi Corporation 功能描述:ATM IMA 80MBPS 2.5V 384BGA - Trays |
| MT90223AG2 | 制造商:Microsemi Corporation 功能描述:ATM IMA 80MBPS 2.5V 384BGA - Trays |
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