參數(shù)資料
型號: MT90221AL
廠商: Mitel Networks Corporation
英文描述: Quad IMA/UNI PHY Device
中文描述: 四IMA的/單向物理層設(shè)備
文件頁數(shù): 70/114頁
文件大小: 304K
代理商: MT90221AL
MT90221
62
Address (Hex):
Direct access
29D
Used to initiate an update of the RX Delay registers based on the link and delay
value to read
00
Reset Value (Hex):
Bit #
Type
Description
7:6
R/W
00: normal delay,
01: read pointer,
10: write pointer.
Writing a 1 will reset the value of the maximum delay over time register for the selected
IMA Group (see bits 1:0).
Delay register:
11: Maximum Delay over time
10: Current Maximum Delay for an IMA Group
01: Current Minimum Delay for an IMA Group
00: Current Delay for a link
Reserved. Write 0 for normal operation.
Bits 1:0 are used to specify the physical link or the IMA Group number.
5
R/W
4:3
R/W
2
R/W
R/W
1:0
Table 67 - RX Delay Select Register
Address (Hex):
Direct access
284
This register contains the delay value (in number of cells) selected by the RX
Delay Select Register. The value always include the current guardband delay
00
Reset Value (Hex):
Bit #
Type
Description
7:6
5:0
R/W
R/W
Unused. Read all 0’s.
Delay Value (MSB)
Table 68 - RX Delay MSB Register
Address (Hex):
Direct access
285
This register contains the delay value (in number of cells) selected by the RX
Delay Select Register. The value always include the current guardband delay.
04
Reset Value (Hex):
Bit #
Type
Description
7:0
R/W
Delay Value (LSB).
Table 69 - RX Delay LSB Register
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