參數(shù)資料
型號: MT49H32M9CFM-xx
廠商: Micron Technology, Inc.
英文描述: 288Mb SIO REDUCED LATENCY(RLDRAM II)
中文描述: 288Mb二氧化硅約化延遲(延遲DRAM二)
文件頁數(shù): 39/44頁
文件大?。?/td> 1117K
代理商: MT49H32M9CFM-XX
16 MEG x 18, 32 MEG x 9
2.5V V
EXT
, 1.8V V
DD
, HSTL, SIO, RLDRAM II
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
39
Table 15:
Identification Register Definitions
INSTRUCTION FIELD
ALL DEVICES
abcd
DESCRIPTION
Revision Number
(31:28)
Device ID
(27:12)
ab = die revision
cd = 10 for x36, 01 for x18, 00 for x9.
def = 000 for 288M, 001 for 576M, 010 for 1G.
i = 0 for common I/O, 1 for separate I/O.
jk = 00 for RLDRAM, 01 for RLDRAM II.
Allows unique identification of RLDRAM vendor.
00jkidef10100111
Micron JEDEC ID
Code (11:1)
ID Register Presence
Indicator (0)
00000101100
1
Indicates the presence of an ID register.
Table 16:
Scan Register Sizes
REGISTER NAME
Instruction
Bypass
ID
Boundary Scan
BIT SIZE
8
1
32
113
Table 17:
Instruction Codes
INSTRUCTION
Extest
CODE
0000 0000
DESCRIPTION
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
This operation does not affect RLDRAM operations.
Loads the ID register with the vendor ID code and places the register between
TDI and TDO. This operation does not affect RLDRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Selects the bypass register to be connected between TDI and TDO. Data driven by
output balls are determined from values held in the boundary scan register.
Selects the bypass register to be connected between TDI and TDO. All outputs are
forced into high impedance state.
Places the bypass register between TDI and TDO. This operation does not affect
RLDRAM operations.
ID Code
0010 0001
Sample/Preload
Clamp
0000 0101
0000 0111
High-Z
0000 0011
Bypass
1111 1111
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