參數(shù)資料
型號: MT49H32M9CFM-xx
廠商: Micron Technology, Inc.
英文描述: 288Mb SIO REDUCED LATENCY(RLDRAM II)
中文描述: 288Mb二氧化硅約化延遲(延遲DRAM二)
文件頁數(shù): 31/44頁
文件大?。?/td> 1117K
代理商: MT49H32M9CFM-XX
16 MEG x 18, 32 MEG x 9
2.5V V
EXT
, 1.8V V
DD
, HSTL, SIO, RLDRAM II
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
31
Figure 33: Mode Register Set Command in Multiplexed Address Mode
The addresses A0, A3, A4, A5, A8, and A9 must be set as follows in order to activate the mode register in the
multiplexed address mode.
NOTE:
1. Bits A(17:10)
must
be set to zero.
2. BL = 8 is not available for configuration 1.
3. ±15% temperature variation.
Figure 34: Power-Up Sequence in Multiplexed Address Mode
The following sequence must be respected in order to power up the RLDRAM in the multiplexed address mode.
NOTE:
1. Address A5 must be set HIGH (muxed address mode setting when RLDRAM is in normal mode of operation).
2. Address A5 must be set HIGH (muxed address mode setting when RLDRAM is already in muxed address mode).
A4
A5
A4
A3
A3
A0
A8
A9
A3x
0
1
BL
4
8
2
A4x
0
1
0
0
1
1
A9
A9y
0
1
A8
A4y A3y A0x
1
1
0
1
Configuration
Configuration
CoRLDRAM
1
2
(default)
1
2
2
reserved
reserved
reserved
not valid
2 (default)
DLL enabled
DLL Reset
DLL Reset
Burst Length
Burst Length
DLL Reset
Address
Mux
Address Mux
DLL reset (default)
3
reserved
1
1
0
1
0
1
0
0
1
0
0
0
1
1
0
0
1
0
1
0
Impedance
Matching
Impedance
Matching
A8x
0
1
Resistor
external
A5x
0
1
nonmultiplexed
(default)
address multiplexed
A9x
0
1
Enabled
Termination
Disabled (default)
On-Die
Termination
On-Die
Termination
Unused
Ax
Ay
internal 50
3
(default)
V
EXT
V
DD
V
DD
Q
V
REF
V
TT
CK#
CK
CMD
200μs MIN
t
MRSC
t
RC
2,048 cycles
MIN
6 × 2,048
cycles MIN
MRS
MRS
MRS
RF0
RF1
RF7
AC
DON’T CARE
ADD
A
1)
MRS
Ax
2)
Ay
t
MRSC
1 cycle
MIN
1 cycle
MIN
MRS: MRS command
RFx: REFRESH Bank x
AC: any command
NOP
NOP
NOP
NOP
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