參數(shù)資料
型號: MT49H32M9CFM-xx
廠商: Micron Technology, Inc.
英文描述: 288Mb SIO REDUCED LATENCY(RLDRAM II)
中文描述: 288Mb二氧化硅約化延遲(延遲DRAM二)
文件頁數(shù): 14/44頁
文件大?。?/td> 1117K
代理商: MT49H32M9CFM-XX
16 MEG x 18, 32 MEG x 9
2.5V V
EXT
, 1.8V V
DD
, HSTL, SIO, RLDRAM II
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_2.fm - Rev. F 11/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
14
Programmable Impedance Output
Buffer
The RLDRAM II is equipped with programmable
impedance output buffers. This allows a user to match
the driver impedance to the system. To adjust the
impedance, an external precision resistor (RQ) is con-
nected between the ZQ ball and V
SS
. The value of the
resistor must be five times the desired impedance. For
example, a 300
resistor is required for an output
impedance of 60
. To ensure that output impedance is
one fifth the value of RQ (within 15 percent), the range
of RQ is 125
to 300
.
Output impedance updates may be required
because, over time, variations may occur in supply
voltage and temperature. The device samples the value
of RQ. An impedance update is transparent to the sys-
tem and does not affect device operation. All data
sheet timing and current specifications are met during
an update.
Clock Considerations
The RLDRAM II utilizes internal delay-locked loops
for maximum output, data valid windows. It can be
placed into a stopped-clock state to minimize power
with a modest restart time of 1,024 cycles.
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