參數(shù)資料
型號(hào)： MT48V16M16LFFG
廠商： Micron Technology, Inc.
英文描述： MOBILE SDRAM
中文描述： 移動(dòng)SDRAM
文件頁數(shù)： 16/58頁
文件大小： 1451K
代理商： MT48V16M16LFFG
16
256Mb: x16 Mobile SDRAM
MobileRamY26L_A.p65 – Pub. 5/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
256Mb: x16
MOBILE SDRAM
ADVANCE
This is shown in Figure 7 for CAS latencies of two and
three; data element
n
+ 3 is either the last of a burst of
four or the last desired of a longer burst. The 256Mb
SDRAM uses a pipelined architecture and therefore
does not require the 2
n
rule associated with a prefetch
Figure 7
Consecutive READ Bursts
architecture. A READ command can be initiated on any
clock cycle following a previous READ command. Full-
speed random read accesses can be performed to the
same bank, as shown in Figure 8, or each subsequent
READ may be performed to a different bank.
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
BANK,
COL
n
NOP
BANK,
COL
b
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
D
OUT
b
READ
X
= 0 cycles
NOTE:
Each READ command may be to either bank. DQM is LOW.
CAS Latency = 1
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
BANK,
COL
n
NOP
BANK,
COL
b
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
D
OUT
b
READ
X
= 1 cycle
CAS Latency = 2
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
BANK,
COL n
NOP
BANK,
COL
b
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
D
OUT
b
READ
NOP
T7
X
= 2 cycles
CAS Latency = 3
DON’T CARE
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