參數(shù)資料
型號(hào)： MSC8103VT1200F
廠商： Freescale Semiconductor
文件頁數(shù)： 56/104頁
文件大?。?/td> 0K
描述： IC DSP 16BIT 300MHZ 332-FCPBGA
標(biāo)準(zhǔn)包裝： 90
系列： StarCore
類型： SC140 內(nèi)核
接口： 通信處理器模塊（CPM）
時(shí)鐘速率： 300MHz
非易失內(nèi)存： 外部
芯片上RAM： 512kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.60V
工作溫度： -40°C ~ 75°C
安裝類型： 表面貼裝
封裝/外殼： 332-BFBGA，F(xiàn)CPBGA
供應(yīng)商設(shè)備封裝： 332-FCBGA（17x17）
包裝： 托盤
AC Timings
MSC8103 Network Digital Signal Processor, Rev. 12
Freescale Semiconductor
2-15
Table 2-16.
AC Timing for SIU Inputs
No.
Characteristic
Value2
Units
10
Hold time for all signals after the 50% level of the DLLIN rising edge
0.5
ns
11a
ABB/AACK set-up time before the 50% level of the DLLIN rising edge
3.5
ns
11b
DBG/DBB/BR/TC set-up time before the 50% level of the DLLIN rising edge
5.0
ns
11c
ARTRY set-up time before the 50% level of the DLLIN rising edge
4.0
ns
11d
TA set-up time before the 50% level of the DLLIN rising edge
Pipeline mode
Non-pipeline mode
3.5
4.0
ns
11e
TEA set-up time before the 50% level of the DLLIN rising edge
Pipeline mode
Non-pipeline mode
4.0
3.0
ns
11f
PSDVAL set-up time before the 50% level of the DLLIN rising edge
Pipeline mode
Non-pipeline mode
3.5
ns
11g
TS set-up time before the 50% level of the DLLIN rising edge
5.0
ns
11h
BG set-up time before the 50% level of the DLLIN rising edge
4.5
ns
12
Data bus set-up time before the 50% level of the DLLIN rising edge in Normal
Pipeline mode
Non-pipeline mode
2.5
5.0
ns
13
Data bus set-up time before the 50% level of the DLLIN rising edge in ECC and PARITY modes
Pipeline mode
Non-pipeline mode
2.5
8.0
ns
14
DP set-up time before the 50% level of the DLLIN rising edge
Pipeline mode
Non-pipeline mode
4.0
9.0
ns
15a
Address bus set-up time before the 50% level of the DLLIN rising edge
Extra cycle mode (SIUBCR[EXDD] = 0)
Non-extra cycle mode (SIUBCR[EXDD] = 1)
5.0
8.0
ns
15b
Address attributes: TT/TBST/TSIZ/GBL set-up time before the 50% level of the DLLIN rising edge
Extra cycle mode (SIUBCR[EXDD] = 0)
Non-extra cycle mode (SIUBCR[EXDD] = 1)
5.0
5.5
ns
161
PUPMWAIT/IRQ signals set-up time before the 50% level of the DLLIN rising edge
3.0
ns
Notes:
1.
The set-up time for these signals is for synchronous operation. Any set-up time can be used for asynchronous operation.
2.
Input specifications are measured from the 50% level of the rising edge of DLLIN to the 50% level of the signal. Timings are
measured at the pin.
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