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| 型號： | MSC8103VT1200F |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 32/104頁 |
| 文件大小： | 0K |
| 描述： | IC DSP 16BIT 300MHZ 332-FCPBGA |
| 標準包裝： | 90 |
| 系列： | StarCore |
| 類型： | SC140 內(nèi)核 |
| 接口： | 通信處理器模塊（CPM） |
| 時鐘速率： | 300MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 512kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.60V |
| 工作溫度： | -40°C ~ 75°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 332-BFBGA，F(xiàn)CPBGA |
| 供應商設備封裝： | 332-FCBGA（17x17） |
| 包裝： | 托盤 |
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CPM Ports
MSC8103 Network Digital Signal Processor, Rev. 12
Freescale Semiconductor
1-29
PC22
SI1: L1ST1
CLK10
DMA: DREQ1
Output
Input
Input/ Output
Serial Interface 1: Layer 1 Strobe 1
The MSC8103 time-slot assigner supports up to four strobe outputs that
can be asserted on a bit or byte basis. The strobe outputs are useful for
interfacing to other devices that do not support the multiplexed interface or
for enabling/disabling three-state I/O buffers in a multiple-transmitter
architecture. These strobes can also generate output wave forms for such
applications as stepper-motor control.
Clock 10
The CPM supports up to 10 clock input pins sent to the bank-of-clocks
selection logic, where they can be routed to the controllers.
DMA: Request 1
DACK1, DREQ1, DRACK1, and DONE1 belong to the SIU DMA controller.
DONE1 and DRACK1 are signals on the same pin and therefore cannot be
used simultaneously. There are two sets of DMA pins associated with the
PIO ports.
PC15
SMC2: SMTXD
SCC1: CTS/CLSN
FCC1: TXADDR0
UTOPIA master
FCC1: TXADDR0
UTOPIA slave
Output
Input
Output
Input
SMC2: Serial Management Transmit Data
The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not
all signals are used for all applications. SMCs are full-duplex ports that
support three protocols or modes: UART, transparent, or general-circuit
interface (GCI). See also PA9.
SCC1: Clear To Send, Collision
Typically used in conjunction with RTS. The MSC8103 SCC1 transmitter
sends out a request to send data signal (RTS). The request is accepted
when CTS is returned low. CLSN is the signal used in Ethernet mode. See
also PC29.
FCC1: UTOPIA Master Transmit Address Bit 0
This is master transmit address bit 0.
FCC1: UTOPIA Slave Transmit Address Bit 0
This is slave transmit address bit 0.
PC14
SI1: L1ST2
SCC1: CD, RENA
FCC1: RXADDR0
UTOPIA master
FCC1: RXADDR0
UTOPIA slave
Output
Input
Output
Input
Serial Interface 1: Layer 1 Strobe 2
The MSC8103 time-slot assigner supports up to four strobe outputs that
can be asserted on a bit or byte basis. The strobe outputs are useful for
interfacing to other devices that do not support the multiplexed interface or
for enabling/disabling three-state I/O buffers in a multiple-transmitter
architecture. These strobes can also be generate output wave forms for
such applications as stepper-motor control.
SCC1: Carrier Detect, Receive Enable
Typically used in conjunction with RTS supported by SCC1. The
MSC8103MSC8103 SCC1 transmitter requests the receiver to send data
by asserting RTS low. The request is accepted when CTS is returned low.
FCC1: UTOPIA Multi-PHY Master Receive Address Bit 0
This is master receive address bit 0.
FCC1: UTOPIA Multi-PHY Slave Receive Address Bit 0
This is slave receive address bit 0.
Table 1-9.
Port C Signals (Continued)
Name
Dedicated
I/O Data
Direction
Description
General-
Purpose I/O
Peripheral Controller:
Dedicated I/O
Protocol
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