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參數(shù)資料
| 型號： | MSC8103VT1200F |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 15/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 16BIT 300MHZ 332-FCPBGA |
| 標準包裝： | 90 |
| 系列： | StarCore |
| 類型： | SC140 內(nèi)核 |
| 接口： | 通信處理器模塊（CPM） |
| 時鐘速率： | 300MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 512kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.60V |
| 工作溫度： | -40°C ~ 75°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 332-BFBGA，F(xiàn)CPBGA |
| 供應商設備封裝： | 332-FCBGA（17x17） |
| 包裝： | 托盤 |
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MSC8103 Network Digital Signal Processor, Rev. 12
1-14
Freescale Semiconductor
Signals/Connections
PSDA10
PGPL0
Output
Bus SDRAM A10
Output from the bus SDRAM controller. This pin is part of the address when a row address is driven.
It is part of the command when a column address is driven.
Bus UPM General-Purpose Line 0
One of six general-purpose output lines of the UPM. The values and timing of this pin are
programmed in the UPM.
PSDWE
PGPL1
Output
Bus SDRAM Write Enable
Output from the bus SDRAM controller. This pin should connect to the SDRAM WE input signal.
Bus UPM General-Purpose Line 1
One of six general-purpose output lines from the UPM. The values and timing of this pin are
programmed in the UPM.
POE
PSDRAS
PGPL2
Output
Bus Output Enable
Output of the bus GPCM. Controls the output buffer of memory devices during read operations.
Bus SDRAM RAS
Output from the bus SDRAM controller. This pin should connect to the SDRAM Row Address Strobe
(RAS) input signal.
Bus UPM General-Purpose Line 2
One of six general-purpose output lines from the UPM. The values and timing of this pin are
programmed in the UPM.
PSDCAS
PGPL3
Output
Bus SDRAM CAS
Output from the bus SDRAM controller. This pin should connect to the SDRAM Column Address
Strobe (CAS) input signal.
Bus UPM General-Purpose Line 3
One of six general-purpose output lines from the UPM. The values and timing of this pin are
programmed in the UPM.
PGTA
PUPMWAIT
PPBS
PGPL4
Input
Output
GPCM TA
Terminates transactions during GPCM operation. Requires an external pull up resistor for proper
operation.
Bus UPM Wait
Input to the UPM. An external device can hold this pin high to force the UPM to wait until the device
is ready for the operation to continue.
Bus Parity Byte Select
In systems that store data parity in a separate chip, this output is the byte-select for that chip.
Bus UPM General-Purpose Line 4
One of six general-purpose output lines from the UPM. The values and timing of this pin are
programmed in the UPM.
PSDAMUX
PGPL5
Output
Bus SDRAM Address Multiplexer
Controls the SDRAM address multiplexer when the MSC8103 is in External Master mode.
Bus UPM General-Purpose Line 5
One of six general-purpose output lines from the UPM. The values and timing of this pin are
programmed in the UPM.
Table 1-6.
Memory Controller Signals (Continued)
Signal
Data Flow
Description
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