參數(shù)資料
型號： MSC8103VT1200F
廠商： Freescale Semiconductor
文件頁數(shù)： 27/104頁
文件大小： 0K
描述： IC DSP 16BIT 300MHZ 332-FCPBGA
標(biāo)準包裝： 90
系列： StarCore
類型： SC140 內(nèi)核
接口： 通信處理器模塊（CPM）
時鐘速率： 300MHz
非易失內(nèi)存： 外部
芯片上RAM： 512kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.60V
工作溫度： -40°C ~ 75°C
安裝類型： 表面貼裝
封裝/外殼： 332-BFBGA，F(xiàn)CPBGA
供應(yīng)商設(shè)備封裝： 332-FCBGA（17x17）
包裝： 托盤
CPM Ports
MSC8103 Network Digital Signal Processor, Rev. 12
Freescale Semiconductor
1-25
PC30
BRG2O
CLK2
Timer1: TOUT1
EXT1
Output
Input
Output
Input
Baud-Rate Generator 2 Output
The CPM supports up to 8 BRGs used internally by the bank-of-clocks
selection logic and/or to provide an output to one of the 8 BRG pins.
Clock 2
The CPM supports up to 10 clock input pins sent to the bank-of-clocks
selection logic, where they can be routed to the controllers.
Timer 1: Timer Out 1
The timers (Timer[1–4]) can output a signal on a timer output (TOUT[1–4])
when the reference value is reached. This signal can be an active-low
pulse or a toggle of the current output. The output can also connect
internally to the input of another timer, resulting in a 32-bit timer.
External Request 1
Asserts an internal request to the CPM processor. The signal can be
programmed as level- or edge-sensitive, and also has programmable
priority. Refer to the RISC Controller Configuration Register (RCCR)
description in the Chapter 17 of the MSC8103 Reference Manual for
programming information. There are no current microcode applications for
this request line. It is reserved for future development.
PC29
BRG3O
CLK3
TIN2
SCC1: CTS, CLSN
Output
Input
Baud-Rate Generator 3 Output
The CPM supports up to 8 BRGs used internally by the bank-of-clocks
selection logic and/or to provide an output to one of the 8 BRG pins.
Clock 3
The CPM supports up to 10 clock input pins sent to the bank-of-clocks
selection logic, where they can be routed to the controllers.
Timer Input 2
A timer can have one of the following sources: another timer, system
clock, system clock divided by 16 or a timer input. The CPM supports up to
4 timer inputs. The timer inputs can be captured on the rising, falling or
both edges.
SCC1: Clear to Send, Collision
Typically used in conjunction with RTS. The MSC8103 SCC1 transmitter
sends out a request to send data signal (RTS). The request is accepted
when CTS is returned low. CLSN is the signal used in Ethernet mode. See
also PC15.
Table 1-9.
Port C Signals (Continued)
Name
Dedicated
I/O Data
Direction
Description
General-
Purpose I/O
Peripheral Controller:
Dedicated I/O
Protocol
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