參數(shù)資料
型號(hào)： MSC8103VT1200F
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 43/104頁(yè)
文件大小： 0K
描述： IC DSP 16BIT 300MHZ 332-FCPBGA
標(biāo)準(zhǔn)包裝： 90
系列： StarCore
類型： SC140 內(nèi)核
接口： 通信處理器模塊（CPM）
時(shí)鐘速率： 300MHz
非易失內(nèi)存： 外部
芯片上RAM： 512kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.60V
工作溫度： -40°C ~ 75°C
安裝類型： 表面貼裝
封裝/外殼： 332-BFBGA，F(xiàn)CPBGA
供應(yīng)商設(shè)備封裝： 332-FCBGA（17x17）
包裝： 托盤
DC Electrical Characteristics
MSC8103 Network Digital Signal Processor, Rev. 12
Freescale Semiconductor
2-3
This section describes the DC electrical characteristics for the MSC8103. The measurements in Table 2-4 assume
the following system conditions:
TJ = 0 – 100 °C
VDD = 1.6 V ± 5% VDC
VDDH = 3.3 V ± 5% VDC
GND = 0 VDC
Note:
The leakage current is measured for nominal VDDH and VDD or both VDDH and VDD must vary in the same
direction (for example, both VDDH and VDD vary by ± 5 percent).
Table 2-4.
DC Electrical Characteristics
Characteristic
Symbol
Min
Max
Unit
Input high voltage1, all inputs except CLKIN
VIH
2.0
3.465
V
Input low voltage1
VIL
GND
0.8
V
CLKIN input high voltage
VIHC
2.5
3.465
V
CLKIN input low voltage2
VILC
GND
0.8
V
Input leakage current, VIN = VDDH
IIN
—10
A
Tri-state (high impedance off state) leakage current,
VIN = VDDH
IOZ
—10
A
Signal low input current3, VIL = 0.8 V
IL
—
–4.0
mA
Signal high input current3, VIH = 2.0 V
IH
—4.0
mA
Output high voltage, IOH = –2 mA, except open drain pins
VOH
2.4
—
V
Output low voltage, IOL= 3.2 mA
VOL
—0.4
V
Notes:
1.
See Figure 2-1 for undershoot and overshoot voltages.
2.
The optimum CLKIN duty cycle is obtained when: VILC = VDDH – VIHC.
3.
Not tested. Guaranteed by design.
Figure 2-1.
Overshoot/Undershoot Voltage for VIH and VIL
Table 2-5.
Typical Power Dissipation
Characteristic
Symbol
Typical
Unit
Core power dissipation at 300 MHz
PCORE
450
mW
CPM power dissipation at 200 MHz
PCPM
320
mW
SIU power dissipation at 100 MHz
PSIU
80
mW
Core leakage power
PLCO
3mW
CPM leakage power
PLCP
6mW
SIU leakage power
PLSI
2mW
GND
GND – 0.3 V
GND – 0.7 V
VIL
VIH
Must not exceed 10% of clock period
VDDH + 20%
VDDH + 10%
VDDH
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