
MOTOROLA
Index
Index-7
INDEX
Internal interrupt destination register,
12-24
Internal interrupt vector priority register,
12-24
Interrupt protocol, EPIC controller,
12-7
IPHPR (inbound post_FIFO head pointer
register),
10-15
IPR (interrupt pending register),
12-9
IPTPR (inbound post_FIFO tail pointer
register),
10-16
IRDY (initiator ready) signal,
3-12
,
8-7
IRQ
n
(discrete interrupt),
3-22
IRR (interrupt request register) register,
12-9
IS (interrupt selector) register,
12-9
ISR (in-service register),
12-9
ITWR (inbound translation window register),
4-14
J
JTAG interface
block diagram of JTAG interface,
15-22
boundary-scan registers,
15-23
bypass register,
15-22
instruction register,
15-23
JTAG registers,
15-22
JTAG signals,
15-22
status register,
15-23
TAP controller,
15-23
L
L_INT (local interrupt) signal,
3-23
Little-endian mode
accessing configuration registers,
5-2
aligned scalars, address modification,
B-6
byte lane translation,
B-7
byte ordering,
B-6
DMA descriptors,
9-11
LE_MODE bit,
5-23
,
B-6
PCI bus,
8-2
,
B-1
PCI I/O space,
B-12
PCI memory space,
B-9
LMBAR (local memory base address
register),
4-13
,
5-14
Load/store
byte-reverse instructions,
A-22
floating-point load instructions,
A-23
floating-point move instructions,
A-23
floating-point store instructions,
A-23
integer load instructions,
A-21
integer store instructions,
A-21
load/store multiple instructions,
A-22
memory synchronization instructions,
A-22
string instructions,
A-22
LOCK signal,
3-12
,
8-26
M
MAA (memory address attribute) signals,
3-27
,
15-1
Master-abort, PCI,
8-15
,
13-9
MCCR
n
(memory control configuration)
registers,
5-41
D
5-50
MCP (machine check),
3-25
Memory data path error capture monitor
register,
15-19
Memory interface
address signals,
6-5
block diagram,
6-3
configuration at reset,
6-6
configuration registers,
5-34
DMA burst wrap,
6-22
ECC error,
13-7
EDO DRAM interface,
6-6
error detection,
13-6
errors within a nibble,
13-7
features list,
1-12
Flash interface,
6-61
Flash write error,
13-6
FPM interface,
6-6
memory attribute signals,
1-19
overview,
1-13
,
6-1
physical memory,
13-7
Port X,
6-72
read data parity error,
13-7
refresh overflow error,
13-8
registers
memory bank enable register,
5-39
memory boundary registers,
5-35
D
memory control configuration registers,
5-41
memory page mode register,
5-40
ROM interface,
6-61
SDRAM interface,
6-31
select error,
13-7
signal summary,
6-4
signals,
3-16
system memory,
13-7
Memory management unit (MMU)
overview,
2-8
,
2-31
Memory page mode register,
5-40
Memory synchronization
instructions,
A-22
Message unit
overview,
1-15
Message unit,
see
I
2
O interface,
10-1
MIV (memory interface valid),
3-28
MIV (memory interface valid) signal,
1-20
,
15-7
Modes
doze mode,
1-18
full-power mode,
1-18
munged little-endian byte ordering,
B-1
nap mode,
1-18