
8-2
MPC8240 Integrated Processor User's Manual
MOTOROLA
PCI Interface Overview
read from local memory, the MPC8240, as a target, can accept the burst-read transfer. When
the MPC8240 is granted mastership of the PCI bus, the burst-write transaction continues.
As an initiator, the MPC8240 supports read and write operations to the PCI memory space,
the PCI I/O space, and the 256-byte PCI conTguration space. As an initiator, the MPC8240
also supports generating PCI special-cycle and interrupt-acknowledge transactions. As a
target, the MPC8240 supports read and write operations to local memory and, in agent
mode, read and write operations to the PCI conTguration space.
The MPC8240 can function as either a PCI host bridge referred to as host mode or a
peripheral device on the PCI bus referred to as agent mode. Note that agent mode is
supported only for address map B. See Section 8.7, òPCI Host and Agent Modes,ó for more
information.
While in agent mode, all of the PCI conTguration registers in the MPC8240 can be
programmed from the PCI bus. However, the PICRs, MICRs, and other conTguration
registers are not accessible from the PCI bus and must be programmed by the processor
core. See Section 8.7.2, òAccessing the MPC8240 ConTguration Space in Agent Mode,ó
for more information.
The PCI interface provides bus arbitration for the MPC8240 and up to Tve other PCI bus
masters. The arbitration algorithm is a programmable two-level round-robin priority
selector. The on-chip PCI arbiter can operate in both host and agent modes or it can be
disabled to allow for an external PCI arbiter.
The MPC8240 also provides an address translation mechanism to map inbound PCI to local
memory accesses and outbound processor core to PCI accesses. Address translation is
required when the MPC8240 is operating in agent mode. Address translation is not
supported in host mode. See Section 8.7.4, òPCI Address Translation Support,ó for more
information.
The interface can be programmed for either little-endian or big-endian formatted data, and
provides data swapping, byte enable swapping, and address translation in hardware. See
Appendix B, òBit and Byte Ordering,ó for more information on the bi-endian features of
the MPC8240.
8.1.1 The MPC8240 as a PCI Initiator
Upon detecting a processor-to-PCI transaction, the MPC8240 requests the use of the PCI
bus. For processor-to-PCI bus write operations, the MPC8240 requests mastership of the
PCI bus when the processor completes the write operation on the internal peripheral logic
bus. For processor-to-PCI read operations, the MPC8240 requests mastership of the PCI
bus when it decodes that the access is for PCI address space.
Once granted, the MPC8240 drives the 32-bit PCI address (AD[31D0]) and the bus
command (C/BE[3D0]) signals. The master interface supports reads and writes of up to
32 bytes without inserting master-initiated wait states.