
MOTOROLA
Chapter 6. MPC8240 Memory Interface
6-67
ROM/Flash Interface Operation
For 32-bit ROMs, the least signiTcant 20 address bits are identical to those previously
described for 64-bit ROMs. However, a 21st address bit, SDMA12/SDBA1 (AR[20]), is
added as the new most signiTcant address bit. Refer to Table 6-2 on page -5 for òMemory
Address Signal Mappings.ó
The MPC8240s two ROM chip select outputs are decoded from the memory address and
can be used as bank selects. The MPC8240 can access 16 Mbytes of ROM in systems that
have a 64-bit memory bus (8 Mbytes in each bank). In this mode, bank select RCS0 decodes
addresses
0xFF800000DFFFFFFFF,
0xFF000000DFF7FFFFF.
and
RCS1
decodes
addresses
Implementations that require less than 16 Mbytes of ROM may allocate the required ROM
to one or both banks. As an example, a 4 Mbyte implementation can place the ROM entirely
within the range of RCS0, (at 0xFFC00000DFFFFFFFF), or can split the ROM between
RCS1 and RCS0, (at 0xFF600000DFF7FFFFF and 0xFFE00000DFFFFFFFF).
The MPC8240 can access 16 Mbytes of ROM in systems that have a 32-bit memory bus (8
Mbytes in each bank). In this mode, bank select RCS0 decodes addresses
0xFF800000DFFFFFFFF, and RCS1 decodes addresses 0xFF000000DFF7FFFFF. As
mentioned previously, implementations that require less than 8 Mbytes of ROM may
allocate the required ROM to one or both banks.
The MPC8240 provides programmable access timing for ROM so that systems of various
clock frequencies may be implemented. The MPC8240 may also be conTgured to take
advantage of burst (or nibble) mode access time improvements which are available with
some ROMs. The programmable parameters for ROM access have granularity of 1 clock
cycle, and are named ROMFAL[0D4] and ROMNAL[0D3] in òMemory Control
ConTguration Register 1: 4 Bytes @ <F0>.ó
ROMFAL represents wait states in the access time for non-bursting ROMs, and also
measures wait states for the Trst data beat from bursting ROMs. If ROMFAL[0D4] is
programmed to 00000, the default access time is 3 clock cycles for 64 or 32 bit read
accesses only and 2 clock cycles for 8 bit read accesses. All write accesses are 2 clock
cycles. Any value speciTed by ROMFAL is added to this default.
ROMNAL represents wait states in access time for nibble (or burst) mode accesses to
bursting ROMs. If ROMNAL[0D3] is programmed to 0000, the default, nibble mode access
time is 2 clock cycles. Any value speciTed by ROMNAL is added to this default. To enable
the burst mode timing capability, memory conTguration register bit òBURST,ó in Table
5-37, must be set by boot code.
ROMFAL and ROMNAL will be conTgured to their maximum value at reset in order to
accommodate initial boot code fetches. The òBURSTó conTguration bit will be cleared at
reset. ROM interface timing conTguration, and use of the ROMFAL and ROMNAL
parameters, is shown in Figure 6-46, Figure 6-47, and Figure 6-48.