MOTOROLA
Contents
xix
CONTENTS
Paragraph
Number
Title
Page
Number
Chapter 14
Power Management
14.1
14.2
14.2.1
14.2.2
14.2.3
14.2.3.1
14.2.3.2
14.2.3.3
14.2.3.4
14.2.3.5
14.2.4
14.3
14.3.1
14.3.1.1
14.3.1.2
14.3.1.3
14.3.1.3.1
14.3.1.3.2
14.3.1.4
14.3.1.4.1
14.3.1.4.2
14.3.1.4.3
14.3.1.4.4
14.4
Overview............................................................................................................14-1
Processor Core Power Management ..................................................................14-1
Dynamic Power Management........................................................................14-2
Programmable Power Modes on Processor Core...........................................14-2
Processor Power Management ModesDetails............................................14-3
Full-Power Mode with DPM Disabled ......................................................14-4
Full-Power Mode with DPM Enabled .......................................................14-4
Processor Doze Mode ................................................................................14-4
Processor Nap Mode..................................................................................14-5
Processor Sleep Mode................................................................................14-5
Power Management Software Considerations...............................................14-6
Peripheral Logic Power Management................................................................14-7
Peripheral Logic Power Modes......................................................................14-7
Peripheral Logic Full Power Mode............................................................14-8
Peripheral Logic Doze Mode.....................................................................14-8
Peripheral Logic Nap Mode.......................................................................14-9
PCI Transactions During Nap Mode......................................................14-9
PLL Operation During Nap Mode.........................................................14-9
Peripheral Logic Sleep Mode.....................................................................14-9
System Memory Refresh during Sleep Mode......................................14-10
Disabling the PLL during Sleep Mode ................................................14-10
PCI Transactions in Sleep Mode..........................................................14-10
SDRAM Paging During Sleep Mode...................................................14-10
Example Code Sequence for Entering Processor Sleep Mode.........................14-11
Chapter 15
Debug Features
15.1
15.1.1
15.1.2
15.1.3
15.1.4
15.2
15.2.1
15.2.2
15.2.3
15.2.4
15.2.5
Address Attribute Signals...................................................................................15-1
Memory Address Attribute Signals (MAA[0D2])..........................................15-1
Memory Address Attribute Signal Timing ....................................................15-2
PCI Address Attribute Signals.......................................................................15-2
PCI Address Attribute Signal Timing............................................................15-3
Memory Debug Address....................................................................................15-4
Enabling Debug Address................................................................................15-4
Debug Address Signal Definitions.................................................................15-4
Physical Address Mappings...........................................................................15-5
RAS/CS Encoding..........................................................................................15-6
Debug Address Timing..................................................................................15-7