
MOTOROLA
Chapter 8. PCI Bus Interface
8-15
PCI Bus Transactions
There are three types of master-initiated termination:
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CompletionCompletion refers to termination when the initiator has concluded its
intended transaction. This is the most common reason for termination.
TimeoutTimeout refers to termination when the initiator loses its bus grant (GNT
is negated), and its internal latency timer has expired. The intended transaction is not
necessarily concluded.
Master-abortMaster-abort is an abnormal case of master-initiated termination. If
no device (including the subtractive decoding agent) asserts DEVSEL to claim a
transaction, the initiator terminates the transaction with a master-abort. For a master-
abort termination, the initiator negates FRAME and then negates IRDY on the next
clock. If a transaction is terminated by master-abort (except for a special-cycle
command), the received master-abort bit (bit 13) of the PCI status register is set.
As an initiator, if the MPC8240 does not detect the assertion of DEVSEL within four clock
cycles following the address phase (Tve clock cycles after asserting FRAME), it terminates
the transaction with a master-abort. On reads that are master-aborted, the MPC8240 returns
all 1s (0xFFFF). On writes that are master-aborted, the data is lost.
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8.4.3.2 Target-Initiated Termination
By asserting the STOP signal, a target may request that the initiator terminate the current
transaction. Once asserted, the target holds STOP asserted until the initiator negates
FRAME. Data may or may not be transferred during the request for termination. If TRDY
and IRDY are asserted during the assertion of STOP, data is transferred. However, if TRDY
is negated when STOP is asserted, it indicates that the target will not transfer any more data;
therefore, the initiator does not wait for a Tnal data transfer as it would in a completion
termination.
When a transaction is terminated by STOP, the initiator must negate its REQ signal for a
minimum of two PCI clock cycles, one being when the bus goes to the idle state (FRAME
and IRDY negated). If the initiator intends to complete the transaction, it can reassert its
REQ immediately following the two clock cycles. If the initiator does not intend to
complete the transaction, it can assert REQ whenever it needs to use the PCI bus again.
There are three types of target-initiated termination:
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DisconnectDisconnect refers to termination requested because the target is
temporarily unable to continue bursting. Disconnect implies that some data has been
transferred. the initiator may restart the transaction at a later time starting with the
address of the next untransferred data. (That is, data transfer may resume where it
left off.)
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RetryRetry refers to termination requested because the target is currently in a state
where it is unable to process the transaction. Retry implies that no data was
transferred. The initiator may start the entire transaction over again at a later time.
Note that the
PCI Local Bus SpeciTcation
, rev 2.1 requires that all retried
transactions must be completed.