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MOTOROLA
Tables
xxvii
TABLES
Table
Number
Title
Page
Number
i
1-1
1-2
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
Acronyms and Abbreviated Terms ................................................................xxxviii
Programmable Processor Power Modes............................................................1-18
Programmable Peripheral Logic Power Modes.................................................1-18
HID0 Field Descriptions....................................................................................2-13
HID0[BCLK] and HID0[ECLK] CKO Signal Configuration...........................2-16
HID1 Field Descriptions....................................................................................2-17
HID2 Field Descriptions....................................................................................2-17
CCU Responses to Processor Transactions.......................................................2-24
Transactions Reflected to the Processor for Snooping......................................2-26
Exception Classifications for the Processor Core..............................................2-28
Exceptions and Conditions ................................................................................2-28
Integer Divide Latency ......................................................................................2-34
Major Differences between MPC8240s Core and the MPC603e Users
Manual.............................................................................................................2-35
MPC8240 Signal Cross Reference.......................................................................3-4
Output Signal States During System Reset..........................................................3-7
PCI Command Encodings....................................................................................3-8
Data Bus Byte Lane Assignments......................................................................3-19
Reset Configuration Signals ..............................................................................3-36
Address Map AProcessor View.......................................................................4-2
Address Map APCI Memory Master View .....................................................4-2
Address Map APCI I/O Master View..............................................................4-2
Address Map BProcessor View.......................................................................4-6
Address Map BPCI Memory Master View (Host Bridge)...............................4-6
Address Map BPCI Memory Master View (Agent Bridge) ............................4-7
Address Map BPCI I/O Master View..............................................................4-8
ATU Register Summary ....................................................................................4-13
Bit Settings for LMBAR0x10........................................................................4-13
Bit Settings for ITWR0x0_2310....................................................................4-14
Bit Settings for OMBAR0x0_2300 ...............................................................4-15
Bit Settings for OTWR0x0_2308..................................................................4-16
Embedded Utilities Local Memory Register Summary.....................................4-18
Embedded Utilities Peripheral Control and Status Register Summary .............4-19
MPC8240 Configuration Registers Accessible from the Processor Core ...........5-4
MPC8240 Configuration Registers Accessible from the PCI Bus......................5-7
PCI Configuration Space Header Summary........................................................5-8
3-1
3-2
3-3
3-4
3-5
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
5-1
5-2
5-3