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參數(shù)資料
| 型號： | MAX1359ACTL+ |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, 0.80 MM HEIGHT, MO220, TQFN-40 |
| 文件頁數(shù)： | 52/74頁 |
| 文件大小： | 1214K |
| 代理商： | MAX1359ACTL+ |
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MAX1358/MAX1359/MAX1360
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
56
______________________________________________________________________________________
The switch-control register controls the two SPDT
switches (SPDT1 and SPDT2) and the two DACA and
DACB output buffer SPST switches (SWA and SWB).
Control these switches by the serial bits in this register,
by any of the UPIO pins that are enabled for that func-
tion, or by the PWM.
SWA: (MAX1358/MAX1359) DACA output buffer SPST-
switch A control bit. The SWA bit, the UPIO inputs (if
configured), and the PWM (if configured) control the
state of the SWA switch as shown in Table 17. The
UPIO_ states of 0 and 1 in the table below correspond
to respective deasserted and asserted logic states as
defined by the ALH_ bit of the UPIO_CTRL register. If a
UPIO is not configured for this mode, its value applied
to the table below is 0. The PWM states of 0 and 1 in the
table below correspond to the respective PWM off (or
low) and on (or high) states defined by the SWAH and
SWAL bits (see the PWM_CTRL Register section). If the
PWM is not configured for this mode, its value applied
to the table below is 0. The power-on default is 0.
SWB: (MAX1358 only) DACB output buffer SPST-switch
B control bit. The SWB bit, the UPIO inputs (if config-
ured), and the PWM (if configured) control the state of
the SWB switch as shown in Table 18. The UPIO_ states
of 0 and 1 in the table correspond to respective
deasserted and asserted logic states as defined by the
ALH_ bit (see the UPIO_CTRL Register section). If a
UPIO is not configured for this mode, its value applied
to the table is 0. The PWM states of 0 and 1 in the table
correspond to the respective PWM off (or low) and on
(or high) states defined by the SWBH and SWBL bits
(see the PWM_CTRL Register section). If the PWM is
not configured for this mode, its value applied to the
table is 0. The power-on default is 0.
SPDT1<1:0>: Single-pole double-throw switch 1 con-
trol bits. The SPDT1<1:0> bits, the UPIO pins (if config-
ured), and the PWM (if configured) control the state of
the switch as shown in Table 19. The UPIO_ states of 0
and 1 in the table below correspond to respective
deasserted and asserted logic states as defined by the
ALH_ bit of the UPIO_CTRL register. If a UPIO is not
configured for this mode, its value applied to Table 19
is 0. The PWM states of 0 and 1 in Table 19 below cor-
respond to the respective PWM off (low) and on (high)
states defined by the SPD1 bit in the PWM_CTRL regis-
ter. If the PWM is not configured for this mode, its value
applied to Table 19 is 0. The power-on default is 00.
MSB
LSB
SWA
SWB
SPDT11
SPDT10
SPDT21
SPDT20
X
SW_CTRL Register (Power-On State: 0000 00XX)
SWA BIT*
UPIO_*
PWM*
SWA SWITCH STATE
000
Switch open
XX
1
Switch closed
X1
X
Switch closed
1X
X
Switch closed
Table 17. SWA States
X = Don’t care.
*Switch SWA control is effectively an OR of the SWA bit, UPIO
pins, and PWM.
SWB BIT*
UPIO_*
PWM*
SWB SWITCH STATE
00
0
Switch open
XX1
Switch closed
X1
X
Switch closed
1X
X
Switch closed
Table 18. SWB States (MAX1358 Only)
X = Don’t care.
*Switch SWB control is effectively an OR of the SWB bit, UPIO
pins, and PWM.
SPDT1<1:0>
UPIO_*
PWM*
SPDT1 SWITCH STATE
00
SNO1 open, SNC1 open
0X
X
1
SNO1 closed, SNC1 closed
0X
1
X
SNO1 closed, SNC1 closed
01
X
SNO1 closed, SNC1 closed
10
00
SNC1 closed, SNO1 open
1X
X1
SNC1 open, SNO1 closed
1X
SNC1 open, SNO1 closed
11
XX
SNC1 open, SNO1 closed
Table 19. SPDT Switch 1 States
X = Don’t care.
*Switch SPDT1 control is effectively an OR of the SPDT10 bit, the
UPIO pins, and the PWM output. The SPDT11 bit determines if
the switches open and close together or if they toggle.
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