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ered by the DVDD monitor in many applications where
DVDD and AVDD are externally connected together.
Multiple supply applications where AVDD and DVDD are
not connected together require a separate external volt-
age monitor for AVDD. See Figure 9 for a block diagram
of the DVDD voltage supervisor.
The second voltage monitor tracks the charge-pump
output voltage, CPOUT. If CPOUT falls below the 2.7V
threshold, a corresponding register status bit (LCPD) is
set to flag the condition. The CPOUT monitor output
can also be mapped to the interrupt generator and out-
put on INT. The CPOUT monitor can be used as a 3V
AVDD monitor in applications where the charge pump is
disabled and CPOUT is connected to AVDD. AVDD
must be greater or equal to DVDD when CPOUT is used
to monitor AVDD. See Figure 10 for a block diagram of
the CPOUT voltage supervisor.
Interrupt Generator (INT)
The interrupt generator provides an interrupt to an
external C. The source of the interrupt is generated by
the status register and can be masked and unmasked
through the IMSK register. CRDY is unmasked by
default and INT is active-high at power-on reset. INT is
programmable as active-high and active-low. Possible
sources include a rising or falling edge of UPIO_, an
RTC alarm, an ADC conversion completion, or the volt-
age-supervisor outputs. The interrupt causes INT to
assert when configured as an interrupt output.
Crystal Oscillator
The on-chip oscillator requires an external crystal (or
resonator) connected between 32KIN and 32KOUT
with a 32.768kHz operating frequency. This oscillator is
used for the RTC, alarm, PWM, watchdog, charge
pump, and FLL. In any crystal-based oscillator circuit,
the oscillator frequency is sensitive to the capacitive
load (CL). CL is the capacitance that the crystal needs
from the oscillator circuit and not the capacitance of the
crystal. The input capacitance across the 32KIN and
32KOUT is 6pF. Choose a crystal with a 32.768kHz
oscillation frequency and a 6pF capacitive load such
as the C-002RX32-E from Epson Crystal. Using a crys-
tal with a CL that is larger than the load capacitance of
the oscillator circuit causes the oscillator to run faster
than the specified nominal frequency of the crystal or to
not start up. See Figures 11 and 12 for block diagrams
of the crystal oscillator and the CLK32K I/O.
MAX1358/MAX1359/MAX1360
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
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29
CMP
ANALOG
2:1 MUX
CONTROL
LOGIC
RESET
DVDD
1.25V
1.8VTH
2.0VTH
LDVD
LSDE
HYSE POR
RSTE
DVDD (1.8V) VOLTAGE MONITOR
WDTO
Figure 9. DVDD Voltage-Supervisor Block Diagram
CMP
CPOUT
1.25V
2.7VTH
LCPD
CPDE
CPOUT (2.7V) VOLTAGE MONITOR
Figure 10. CPOUT Voltage-Supervisor Block Diagram