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參數(shù)資料
| 型號： | MAX1359ACTL+ |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, 0.80 MM HEIGHT, MO220, TQFN-40 |
| 文件頁數(shù)： | 20/74頁 |
| 文件大?。?/td> | 1214K |
| 代理商： | MAX1359ACTL+ |
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offset (i.e., unipolar clipping near zero can be removed).
Perform ADC calibration whenever the ADC configura-
tion, temperature, or AVDD changes. The ADC-done sta-
tus can be programmed to provide an interrupt on INT
or on any UPIO_.
PGA Gain
An integrated PGA provides four selectable gains: +1V/V,
+2V/V, +4V/V, and +8V/V to maximize the dynamic range
of the ADC. Bits GAIN1 and GAIN0 set the gain (see the
ADC Register for more information). The PGA gain is
implemented in the digital filter of the ADC.
ADC Modulator
The MAX1358/MAX1359/MAX1360 perform analog-to-
digital conversions using a single-bit, 3rd-order,
switched-capacitor sigma-delta modulator. The sigma-
delta modulation converts the input signal into a digital
pulse train whose average duty cycle represents the dig-
itized signal information. The pulse train is then
processed by a digital decimation filter. The modulator
provides 2nd-order frequency shaping of the quantiza-
tion noise resulting from the single-bit quantizer. The
modulator is fully differential for maximum signal-to-noise
ratio and minimum susceptibility to power-supply noise.
Signal-Detect Comparator
INT asserts (and remains asserted) within 30s when
the differential voltage on the selected analog inputs
exceeds the signal-detect comparator trip threshold.
The signal-detect comparator’s differential input trip
threshold (i.e., offset) is user selectable and can be pro-
grammed to the following values: 0mV, 50mV, 100mV,
150mV, or 200mV.
Analog Inputs
The ADC provides two external analog inputs: AIN1
and AIN2. The rail-to-rail inputs accept differential or
single-ended voltages, or external temperature-sensing
diodes. The unused op amps, switches, or DAC inputs
and output pins can also be used as rail-to-rail analog
inputs if the associated function is disabled.
Analog Input Protection
Internal protection diodes clamp the analog inputs to
AVDD and AGND, and allow the channel input to swing
from (AGND - 0.3V) to (AVDD + 0.3V). For accurate
conversions near full scale, the inputs must not exceed
AVDD by more than 50mV or be lower than AGND by
50mV. If the inputs exceed (AGND - 0.3V) to (AVDD +
0.3V), limit the current to 50mA.
Analog Mux
The MAX1358/MAX1359/MAX1360 include a dual 10:1
mux for the positive and negative inputs of the ADC.
Figures 3, 4, and 5 illustrate which signals are present at
the inputs of each mux for the MAX1358/MAX1359/
MAX1360. The MUXP[3:0] and MUXN[3:0] bits of the mux
register select the input to the ADC and the signal-detect
comparator (Tables 8 and 9). See the mux register
description in the Register Definitions section for multi-
plexer functionality. The POL bit of the ADC register
swaps the polarity of mux output signals to the ADC.
Digital Filtering
The MAX1358/MAX1359/MAX1360 contain an on-chip
digital lowpass filter that processes the data stream
from the modulator using a SINC4 (sinx/x)4 response.
The SINC4 filter has a settling time of four output data
periods (4 x 200ms).
The MAX1358/MAX1359/MAX1360 have 25% overrange
capability built into the modulator and digital filter:
Figure 6 shows the filter frequency response. The
SINC4 characteristic -3dB cutoff frequency is 0.228
times the first notch frequency.
The output data rate for the digital filter corresponds
with the positioning of the first notch of the filter’s fre-
quency response. The notches of the SINC4 filter are
repeated at multiples of the first notch frequency. The
SINC4 filter provides an attenuation of better than
100dB at these notches. For example, 50Hz is equal to
five times the first notch frequency and 60Hz is equal to
six times the first notch frequency.
Hf
N
SIN N
f
SIN
f
m
()
=
1
4
π
MAX1358/MAX1359/MAX1360
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
______________________________________________________________________________________
27
FREQUENCY (Hz)
GAIN
(dB)
100
80
60
40
20
-160
-120
-80
-40
0
-200
0120
Figure 6. Filter Frequency Response
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