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  • 參數(shù)資料
    型號: MAX1359ACTL+
    廠商: MAXIM INTEGRATED PRODUCTS INC
    元件分類: 模擬信號調(diào)理
    英文描述: SPECIALTY ANALOG CIRCUIT, QCC40
    封裝: 6 X 6 MM, 0.80 MM HEIGHT, MO220, TQFN-40
    文件頁數(shù): 25/74頁
    文件大小: 1214K
    代理商: MAX1359ACTL+
    High-Frequency Clock
    An internal oscillator and a frequency-locked loop (FLL)
    are used to generate a 4.9152MHz ±1% high-frequen-
    cy clock. This clock and derivatives are used internally
    by the ADC, analog switches, and PWM. This clock sig-
    nal outputs to CLK. When the FLL is enabled, the high-
    frequency clock is locked to the 32.768kHz reference. If
    the FLL is disabled, the high-frequency clock is free-
    running. At power-up, the CLK pin defaults to a
    2.4576MHz clock output, which is compatible with most
    Cs. See Figure 14 for a block diagram of the high-fre-
    quency clock.
    User-Programmable I/Os
    The MAX1358/MAX1359/MAX1360 provide four digital
    programmable I/Os (UPIO1–UPIO4). Configure UPIOs
    as logic inputs or outputs using the UPIO control regis-
    ter. Configure the internal pullups using the UPIO setup
    register, if required. At power-up, the UPIO’s are inter-
    nally pulled up to DVDD. UPIO_ outputs can be refer-
    enced to DVDD or CPOUT. See the UPIO__CTRL
    Register and UPIO_SPI Register sections for more
    details on configuring the UPIO_ pins.
    Program each UPIO1–UPIO4 as one of the following:
    General-purpose input
    Power-mode control
    Analog switch (SPST) and SPDT control input
    ADC data-ready output
    General-purpose output
    PWM output
    Alarm output
    SPI passthrough
    MAX1358/MAX1359/MAX1360
    16-Bit Data-Acquisition Systems with ADC, DACs,
    UPIOs, RTC, Voltage Monitors, and Temp Sensor
    ______________________________________________________________________________________
    31
    M32K
    TUNE<8:0>
    HFCE
    FLLE
    CRDY
    HFCLK
    1, 2, 4, 8
    DIVIDER
    2:1
    MUX
    CLK
    CLKE
    CKSEL<1:0>
    CKSEL2
    1
    0
    4.9152MHz HF OSCILLATOR AND FLL
    4.9152MHz
    32.768kHz
    FREQUENCY
    COMPARE
    FREQ
    ERROR
    DIGITALLY
    CONTROLLED
    OSCILLATOR
    FREQUENCY
    INTEGRATOR
    Figure 14. High-Frequency Clock and FLL Block Diagram
    Figure 15. Temperature-Sensor Measurement Block Diagram
    CURRENT
    SOURCE
    1:3
    DEMUX
    IVAL<1:0>
    IMUX<1:0>
    AIN1
    AIN2
    AIN1
    AIN2
    TEMP+
    TEMP-
    PROGRAMMABLE CURRENT SOURCE
    TEMP SENSOR
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