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參數(shù)資料
| 型號： | MAX1359ACTL+ |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, 0.80 MM HEIGHT, MO220, TQFN-40 |
| 文件頁數(shù)： | 28/74頁 |
| 文件大?。?/td> | 1214K |
| 代理商： | MAX1359ACTL+ |
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MAX1358/MAX1359/MAX1360
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
34
______________________________________________________________________________________
in a respective 1.25V, 2.048V, or 2.5V reference voltage
at REF. The ADC and DACs use this reference voltage.
The state of the internal voltage reference output buffer at
POR is disabled so it can be driven, at REF, with an exter-
nal reference between AGND and AVDD. The A-grade
reference has an initial tolerance of ±1%. The B-grade
reference has an initial tolerance of ±3%. Program the
reference buffer through the serial interface. Bypass REF
with a 4.7F capacitor to AGND.
Operational Amplifiers (Op Amps)
The MAX1358 includes one uncommitted op amp; the
MAX1359 includes two op amps; and the MAX1360
includes three op amps. These op amps feature rail-to-rail
outputs, near rail-to-rail inputs, and have an 80kHz (1nF
load) input bandwidth. The DACA_OP (DACB_OP) regis-
ter controls the power state of the op amps. When pow-
ered down, the outputs of the op amps are high
impedance.
Single-Pole/Double-Throw (SPDT) Switches
The MAX1358/MAX1359/MAX1360 provide two uncom-
mitted SPDT switches. Each switch has a typical on-resis-
tance of 35
. Control the switches through the SW_CTRL
register, the PWM output, and/or a UPIO port configured
to control the switches (UPIO1–UPIO4_CTRL register).
Pulse-Width Modulator (PWM)
A single 8-bit PWM is available for various system tasks
such as LCD bias control, sensor bias voltage trim,
buzzer drive, and duty-cycled sleep-mode power-con-
trol schemes. PWM input clock sources include the
4.9512MHz FLL output, the 32kHz clock, and frequen-
cy-divided versions of each. Although most Cs have
built-in PWM functions, the MAX1358/MAX1359/
MAX1360 PWM is more flexible by allowing the UPIO
outputs to be driven to DVDD or regulated CPOUT
logic-high voltage levels. For duty-cycled power-control
schemes, use the 32kHz-derived input clock. The PWM
output is available independent of C power state. The
FLL is typically disabled in sleep-override mode.
Serial Interface
The MAX1358/MAX1359/MAX1360 feature a 4-wire serial
interface consisting of a chip select (
CS), serial clock
(SCLK), data in (DIN), and data out (DOUT).
CS must be
low to allow data to be clocked into or out of the device.
DOUT is high impedance while
CS is high. The data is
clocked in at DIN on the rising edge of SCLK. Data is
clocked out at DOUT on the falling edge of SCLK. The
serial interface is compatible with SPI modes CPOL = 0,
CPHA = 0 and CPOL = 1, CPHA = 1. A write operation to
the MAX1358/MAX1359/MAX1360 takes effect on the last
rising edge of SCLK. If
CS goes high before the complete
transfer, the write is ignored. Every data transfer is initiat-
ed by the command byte. The command byte consists of
a start bit (MSB), R/
W bit, and 6 address bits. The start bit
must be 1 to perform data transfers to the device. Zeros
clocked in are ignored. For SPI passthrough mode, see
the UPIO_SPI register. An address byte identifies each
register. Table 4 shows the complete register address
map for this family of DAS. Figures 16, 17, and 18 provide
timing diagrams for read and write commands.
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相關代理商/技術參數(shù) |
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| MAX1359ACTL+ | 制造商:Maxim Integrated Products 功能描述:DATA ACQ SYS SGL ADC SGL DAC 16BIT 40TQFN EP - Rail/Tube |
| MAX1359ACTL+T | 制造商:Maxim Integrated Products 功能描述:DATA ACQ SYS SGL ADC SGL DAC 16BIT 40TQFN EP - Tape and Reel |
| MAX1359ACTL-T | 制造商:Maxim Integrated Products 功能描述:16-BIT DATA-ACQUISITION SYSTEM W ADC,DACS,UPI - Tape and Reel |
| MAX1359AEGL | 制造商:Maxim Integrated Products 功能描述:- Rail/Tube |
| MAX1359AETL | 制造商:Maxim Integrated Products 功能描述:16-BIT DATA-ACQUISITION SYSTEM W ADC,DACS,UPI - Rail/Tube |
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