參數(shù)資料
型號： MAX1359ACTL+
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, QCC40
封裝： 6 X 6 MM, 0.80 MM HEIGHT, MO220, TQFN-40
文件頁數(shù)： 51/74頁
文件大?。?/td> 1214K
代理商： MAX1359ACTL+
MAX1358/MAX1359/MAX1360
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
______________________________________________________________________________________
55
UPIO SPI pass-through control register. These bits map
the serial interface signals to the UPIO pins, allowing
the DAS (MAX1358/MAX1359/MAX1360) to drive other
devices at CPOUT or DVDD voltage levels, depending
on the SV_ bit setting found in the UPIO_CTRL register.
Individual bits are provided to set only the desired
UPIO inputs to the SPI pass-through mode. This mode
becomes active when
CS is driven high to complete the
write to this register, and remains active as long as
CS
stays high (i.e., multiple pass-through writes are possi-
ble). The SPI pass-through mode is deactivated imme-
diately when
CS is pulled low for the next DAS
(MAX1358/MAX1359/MAX1360) write.
The UPIO_ state (both before and after the SPI pass-
through mode) is set by the UP_MD<3:0> and LL_ bits.
When a UPIO is configured for SPI pass-through mode
and the
CS is high, UPR_, UPF_, and LL_ continue to
detect UPIO_ edges, which can still generate interrupts.
See Figure 20 for an SPI pass-through timing diagram.
UP4S: UPIO4 SPI pass-through-mode enable bit. A
logic 1 maps the inverted
CS signal to the UPIO4 pin.
Therefore, UPIO4 is low (near DGND) when SPI pass-
through mode is active, and is high (near DVDD or
CPOUT) when the mode is inactive. A logic 0 disables
the UPIO4 SPI pass-through mode. The power-on
default is 0.
UP3S: UPIO3 SPI pass-through-mode enable bit. A
logic 1 maps the SCLK signal to UPIO3 (directly with no
inversion), while a logic 0 disables the UPIO3 SPI pass-
through mode. The power-on default is 0.
UP2S: UPIO2 SPI pass-through-mode enable bit. A
logic 1 maps the DIN signal to UPIO2 (directly with no
inversion), while a logic 0 disables the UPIO2 SPI pass-
through mode. The power-on default is 0.
UP1S: UPIO1 SPI pass-through-mode enable bit. A
logic 1 maps the UPIO1 input signal to DOUT (directly
with no inversion), while a logic 0 disables the UPIO1
SPI pass-through mode. The power-on default is 0.
MSB
LSB
UP4S
UP3S
UP2S
UP1S
X
UPIO_SPI Register (Power-On State: 0000 XXXX)
CS
WRITE TO DAS TO ENABLE SPI MODE
WRITE THROUGH DAS TO UPIO DEVICE
NORMAL WRITE TO DAS
SCLK
DIN
DN
DN-1 DN-2 DN-3
D3
D2
D1
D0
EN
EN-1 EN-2 EN-3
X
EN
EN-1 EN-2 EN-3
X
D7
D6
D5
D4
D3
D2
D1
D0
DOUT
E3
E2
E1
E0
E3
E2
E1
E0
UPIO4
SET BY UPIO4_CTRL REGISTER
UPIO3
SET BY UPIO3_CTRL REGISTER
UPIO2
SET BY UPIO2_CTRL REGISTER
UPIO1
SET BY UPIO1_CTRL REGISTER
Figure 20. SPI Pass-Through Timing Diagram
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