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參數(shù)資料
| 型號： | MAX1359ACTL+ |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, 0.80 MM HEIGHT, MO220, TQFN-40 |
| 文件頁數(shù)： | 21/74頁 |
| 文件大?。?/td> | 1214K |
| 代理商： | MAX1359ACTL+ |
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MAX1358/MAX1359/MAX1360
Force-Sense DAC (MAX1358/MAX1359)
The MAX1358 incorporates two 10-bit force-sense
DACs and the MAX1359 has one. The DACs’ reference
voltage sets the full-scale range. Program the
DACA_OP and DACB_OP registers using the serial
interface to set the output voltages of the DACs at
OUTA and OUTB. Shorting FBA/B and OUTA/B config-
ures the DAC in a unity-gain setting. Connecting resis-
tors in a voltage-divider configuration between
OUTA/B, FBA/B, and GND sets a different closed-loop
gain for the output amplifier (see the Applications
Information section).
The DAC output amplifier typically settles to ±0.5 LSB
from a full-scale transition within 50s (unity gain and
loaded with 10k
in parallel with 200pF). Loads of less
than 1k
may degrade performance. See the Typical
Operating Characteristics for the source-and-sink
capability of the DAC output.
The MAX1358/MAX1359 feature a software-program-
mable shutdown mode for the DACs. Power down
DACA or DACB independently or simultaneously by
clearing the DAE and DBE bits (see the DACA_OP
Registers and DACB_OP Registers sections). DAC out-
puts OUTA and OUTB go high impedance when pow-
ered down. The DACs are normally powered down at
power-on reset.
Charge Pump
The charge pump provides >3V at CPOUT with a maxi-
mum 10mA load. Enable the charge pump through the
PS_VMONS register. The charge pump is powered
from DVDD. See Figures 7 and 8 for block diagrams of
the charge pump and linear regulator. The charge
pump is disabled at power-on reset.
An internal clock drives the charge-pump clock and
ADC clock. The charge pump delivers a maximum
10mA of current to external devices. The droop and the
ripple depend on the clock frequency (fCLK =
32.768kHz / 2), switch resistances (RSWITCH = 5
),
and the external capacitors (10F) along with their
respective ESRs, as shown below.
Voltage Supervisors
The MAX1358/MAX1359/MAX1360 provide voltage
supervisors to monitor DVDD and CPOUT. The first
supervisor monitors the DVDD supply voltage. RESET
asserts and sets the corresponding LDVD status bit
when DVDD falls below the 1.8V threshold voltage. When
the DVDD supply voltage rises above the threshold dur-
ing power-up,
RESET deasserts after a nominal 1.5s
timeout period to give the crystal oscillator time to stabi-
lize. Set the threshold hysteresis using the HYSE bit of
the PS_VMONS register. See the PS_VMONS Register
section for configuring hysteresis. There is no separate
voltage monitor for AVDD, but the analog supply is cov-
VI
R
fC
R
ESR
V
I
fC
I
ESR
DROOP
OUT OUT
OUT
CLK F
SWITCH
C
RIPPLE
OUT
CLK CPOUT
OUT
C
F
CPOUT
=
=+
+
=+
1
24
2
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
28
______________________________________________________________________________________
OP
1.22V
1.65V
LINEAR 1.65V VOLTAGE REGULATOR
DVDD
REG
LDOE
Figure 7. Linear-Regulator Block Diagram
CF+
CF-
CPOUT
REG
M32K
CHARGE-PUMP DOUBLER
NONOVERLAP
CLOCK GENERATOR
CPE
Figure 8. Charge-Pump Block Diagram
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1359ACTL+ | 制造商:Maxim Integrated Products 功能描述:DATA ACQ SYS SGL ADC SGL DAC 16BIT 40TQFN EP - Rail/Tube |
| MAX1359ACTL+T | 制造商:Maxim Integrated Products 功能描述:DATA ACQ SYS SGL ADC SGL DAC 16BIT 40TQFN EP - Tape and Reel |
| MAX1359ACTL-T | 制造商:Maxim Integrated Products 功能描述:16-BIT DATA-ACQUISITION SYSTEM W ADC,DACS,UPI - Tape and Reel |
| MAX1359AEGL | 制造商:Maxim Integrated Products 功能描述:- Rail/Tube |
| MAX1359AETL | 制造商:Maxim Integrated Products 功能描述:16-BIT DATA-ACQUISITION SYSTEM W ADC,DACS,UPI - Rail/Tube |
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