參數(shù)資料
型號(hào)： MAX1359ACTL+
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, QCC40
封裝： 6 X 6 MM, 0.80 MM HEIGHT, MO220, TQFN-40
文件頁(yè)數(shù)： 19/74頁(yè)
文件大?。?/td> 1214K
代理商： MAX1359ACTL+
MAX1358/MAX1359/MAX1360
ous conversions at 10sps or single conversions at the
40sps setting (effectively 10sps due to four sample
sigma-delta settling), the ADC has 16-bit noise-free res-
olution. The noise-free resolution drops to 10 bits at the
maximum sampling rate of 512sps. Differential inputs
support unipolar (between 0 and VREF) and bipolar
(between ±VREF) modes of operation. Note: Avoid
combinations of input signal and PGA gains that
exceed the reference range at the ADC input. The
ADOU bit in the status register indicates if the ADC has
over-ranged or under-ranged.
Zero-scale and full-scale calibrations remove offset and
gain errors. Direct access to gain and zero-scale cali-
bration registers allows system-level offset and gain cal-
ibration. The zero-scale adjustment register allows
intentional positive offset skewing to preserve unipolar-
mode resolution for signals that have a slight negative
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
26
______________________________________________________________________________________
TEMP
SENSOR
REF
AGND
OUT3
OUT2
SCM2
OUT1
AGND
REF
INM1
IN2-
SCM1
IN3-
AIN1
SNO1
SNC1
TEMP+
TEMP-
SNO2
SNC2
AIN2
10:1
MUX
NEG
10:1
MUX
POS
Av = 1, 2, 4, 8 V/V
POLARITY
FLIPPER
PROG. Vos
PGA
Av = 1, 1.6384, 2 V/V
UPIO
DGND
AGND
AVDD
DVDD
SERIAL
INTERFACE
DIN
CS
DOUT
SCLK
1.25V BANDGAP
REF
16-BIT ADC
IN+
IN-
REF
OP1
IN3+
IN3-
OP3
OUT3
PGA
OUT1
SNO1
SNC1
SCM1
CMP
UPIO1
UPIO2
UPIO3
UPIO4
32.768kHz
OSCILLATOR
32KIN
32KOUT
WATCHDOG
TIMER
4.9152MHz HF
OSCILLATOR
AND FLL
CLK
CLK32K
AIN2
AIN1
INTERRUPT
INT
PWM
CLK32K
INPUT/OUTPUT
CONTROL
DVDD (1.8V)
VOLTAGE
MONITOR
RTC AND
ALARM
SNO2
SNC2
SCM2
CHARGE-
PUMP
DOUBLER
CF+
CF-
IN1-
IN1+
PROG
CURRENT
SOURCE
TEMP+
TEMP-
32K
AIN2
AIN1
CPOUT (2.7V)
VOLTAGE
MONITOR
LINEAR 1.65V
VOLTAGE
REGULATOR
CPOUT
REG
STATUS
4
RESET
LDVD
ALD
CRDY
SDC
ADD
ADOU
UPR<4:1>
4
UPF<4:1>
LCPD
16
CONTROL
LOGIC
HFCLK
M32K
HFCLK
WDTO
DVDD
MAX1360
OP2
OUT2
IN2-
IN2+
SPDT1
SPDT2
Figure 5. MAX1360 Functional Diagram
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