參數(shù)資料
型號： M7A3PE600-FPQG208I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PQFP208
封裝： 0.50 MM PITCH, GREEN, PLASTIC, QFP-208
文件頁數(shù)： 87/168頁
文件大?。?/td> 1335K
代理商： M7A3PE600-FPQG208I
ProASIC3E Flash Family FPGAs
A d v an c ed v0 . 5
2-13
Clock Conditioning Circuits
Overview of Clock Conditioning Circuitry
In ProASIC3E devices, the CCCs are used to implement
frequency
division,
frequency
multiplication,
phase
shifting, and delay operations.
The CCCs are available in six chip locations—each of the
four chip corners and the middle of the east and west
chip sides.
Each CCC can implement up to three independent global
buffers (with or without programmable delay), or a PLL
function (programmable frequency division/multiplication,
phase shift, and delays) with up to three global outputs.
Unused global outputs of a PLL can be used to
implement
independent
global
buffers,
up
to
a
maximum of three global outputs for a given CCC.
A global buffer can be placed in any of the three global
locations (CLKA-GLA, CLKB-GLB, or CLKC-GLC) of a given
CCC.
A PLL macro uses the CLKA CCC input to drive its reference
clock. It uses the GLA and optionally the GLB and GLC
global outputs to drive the global networks. A PLL macro
can also drive the YB and YC regular core outputs. The
GLB (or GLC) global output cannot be reused if the YB (or
YC) output is used (Figure 2-13 on page 2-14). Refer to
information.
Each global buffer, as well as the PLL reference clock, can
be driven from one of the following:
Three
dedicated
single-ended
I/Os
using
a
hardwired connection
Two dedicated differential I/Os using a hardwired
connection
The FPGA core
The CCC block is fully configurable, either via Flash
configuration bits set in the programming bitstream or
through an asynchronous interface. This asynchronous
interface is dynamically accessible from inside the
ProASIC3E device to permit parameter changes (such as
divide ratios) during device operation. To increase the
versatility and flexibility of the clock conditioning
system, the CCC configuration is determined either by
the user during the design process, with configuration
data being stored in Flash memory as part of the device
programming procedure, or by writing data into a
dedicated shift register during normal device operation.
This latter mode allows the user to dynamically
reconfigure
the
CCC
without the
need for
core
programming. The shift register is accessed through a
simple serial interface. Refer to the UJTAG Applications
in ProASIC3/E Devices application note and the "CCC
information.
Global Buffers with No Programmable Delays
The CLKBUF and CLKBUF_LVPECL/LVDS/BLVDS/M-LVDS
macros are composite macros that include an I/O macro
driving a global buffer, which uses a hardwired
connection.
The CLKBUF, CLKBUF_LVPECL/LVDS/BLVDS/M-LVDS, and
CLKINT macros are pass-through clock sources and do
not use the PLL or provide any programmable delay
functionality.
The CLKINT macro provides a global buffer function
driven by the FPGA core.
Many specific CLKBUF macros support the wide variety of
single-ended and differential I/O standards supported by
ProASIC3E devices. The available CLKBUF macros are
Global Buffer with Programmable Delay
The CLKDLY macro is a pass-through clock source that
does not use the PLL, but provides the ability to delay the
clock input using a programmable delay. The CLKDLY
macro takes the selected clock input and adds a user-
defined delay element. This macro generates an output
clock phase shift from the input clock.
The CLKDLY macro can be driven by an INBUF* macro to
create a composite macro, where the I/O macro drives
the global buffer (with programmable delay) using a
hardwired connection. In this case, the I/O must be
placed in one of the dedicated global I/O locations.
Many specific INBUF macros support the wide variety of
single-ended and differential I/O standards supported by
the ProASIC3E family. The available INBUF macros are
The CLKDLY macro can be driven directly from the FPGA
core.
The CLKDLY macro can also be driven from an I/O that is
routed through the FPGA regular routing fabric. In this
case, users must instantiate a special macro, PLLINT, to
differentiate
from
the
hardwired
I/O
connection
described earlier.
The visual CLKDLY configuration in the SmartGen part of
the Libero IDE and Designer tools allows the user to
select the desired amount of delay and configures the
delay elements appropriately. SmartGen also allows the
user to select the input clock source. SmartGen will
automatically instantiate the special macro, PLLINT,
when needed.
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