參數(shù)資料
型號： M7A3PE600-FPQG208I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PQFP208
封裝： 0.50 MM PITCH, GREEN, PLASTIC, QFP-208
文件頁數(shù)： 46/168頁
文件大?。?/td> 1335K
代理商： M7A3PE600-FPQG208I
ProASIC3E Flash Family FPGAs
2- 2
A dvanced v0. 5
Device Overview
The ProASIC3E device family consists of five distinct
programmable architectural features (Figure 2-2):
Core Architecture
VersaTile
The proprietary ProASIC3E family architecture provides
granularity comparable to gate arrays. The ProASIC3E
device core consists of a sea-of-VersaTiles architecture.
As illustrated in Figure 2-3 on page 2-3, there are four
inputs in a logic VersaTile cell, and each VersaTile can be
configured
using
the
appropriate
Flash
switch
connections:
Any three-input logic function
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set (on a fourth
input)
VersaTiles can flexibly map the logic and sequential gates
of a design. The inputs of the VersaTile can be inverted
(allowing bubble pushing), and the output of the tile can
connect to high-speed, very-long-line routing resources.
VersaTiles and larger functions can be connected with
any of the four levels of routing hierarchy.
When the VersaTile is used as an enable D-flip-flop, SET/
CLR is supported by a fourth input. The SET/CLR signal
can only be routed to this fourth input over the VersaNet
(global) network. However, if in the user’s design the
SET/CLR signal is not routed over the VersaNet network,
a compile warning message will be given and the
intended logic function will be implemented by two
VersaTiles instead of one.
The output of the VersaTile is F2 (Figure 2-3 on page 2-3)
when the connection is to the ultra-fast local lines, or YL
when the connection is to the efficient long-line or very-
long-line resources.
Figure 2-2 Device Architecture Overview
4,608-Bit Dual-Port SRAM
or FIFO Block
VersaTile
RAM Block
CCC
I/Os
4,608-Bit Dual-Port SRAM
or FIFO Block
ISP AES
Decryption
User Nonvolatile
FlashROM
Charge Pumps
Bank 0
Bank
7
Bank
6
Bank
3
Bank
2
Bank 1
Bank 5
Bank 4
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