參數(shù)資料
型號： M7A3PE600-FPQG208I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PQFP208
封裝： 0.50 MM PITCH, GREEN, PLASTIC, QFP-208
文件頁數(shù)： 36/168頁
文件大?。?/td> 1335K
代理商： M7A3PE600-FPQG208I
ProASIC3E Flash Family FPGAs
3- 62
Advanced v0.5
Timing Characteristics
VersaTile Specifications as a Sequential Module
The ProASIC3E library offers a wide variety of sequential cells including flip-flops and latches. Each have a data input
and optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample
from the library. For more details, refer to the ProASIC3/E Macro Library Guide.
Table 3-89 Combinatorial Cell Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V
Combinatorial Cell
Equation
Parameter
–2
–1
Std.
–F
Units
INV
Y = !A
tPD
0.40
0.45
0.53
0.64
ns
AND2
Y = A B
tPD
0.46
0.52
0.62
0.74
ns
NAND2
Y = !(A B)
tPD
0.46
0.52
0.62
0.74
ns
OR2
Y = A + B
tPD
0.47
0.54
0.63
0.76
ns
NOR2
Y = !(A + B)
tPD
0.47
0.54
0.63
0.76
ns
XOR2
Y = A
⊕ Bt
PD
0.72
0.82
0.96
1.15
ns
MAJ3
Y = MAJ (A , B, C)
tPD
0.67
0.76
0.90
1.08
ns
XOR3
Y = A
⊕ B ⊕ Ct
PD
0.85
0.97
1.14
1.37
ns
MUX2
Y = A !S + B S
tPD
0.49
0.56
0.65
0.79
ns
AND3
Y = A B C
tPD
0.54
0.62
0.73
0.87
ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
Figure 3-35 Sample of Sequential Cells
DQ
DFN1
Data
CLK
Out
D
Q
DFN1C1
Data
CLK
Out
CLR
DQ
DFI1E1P1
Data
CLK
Out
En
PRE
D
Q
DFN1E1
Data
CLK
Out
En
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