參數(shù)資料
型號： M7A3PE600-FPQG208I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PQFP208
封裝： 0.50 MM PITCH, GREEN, PLASTIC, QFP-208
文件頁數(shù)： 50/168頁
文件大?。?/td> 1335K
代理商： M7A3PE600-FPQG208I
ProASIC3E Flash Family FPGAs
A d v an c ed v0 . 5
3-75
Timing Characteristics
Figure 3-50 FIFO FULL Flag and AFULL Flag Deassertion
RCLK
WA/RA
(Address Counter) MATCH (FULL)
NO MATCH
Dist = AFF_TH - 1
NO MATCH
WCLK
FULL
1st rising
edge
after 1st
read
1st rising
edge
after 2nd
read
t
WCKF
tCKAF
AFULL
Table 3-96 FIFO
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
–2
–1
Std.
–F
Units
tENS
REN_B,WEN_B Setup time
0.28
0.32
0.38
0.45
ns
tENH
REN_B, WEN_B Hold time
0.00
ns
tBKS
BLK_B Setup time
0.25
0.29
0.34
0.40
ns
tBKH
BLK_B Hold time
0.00
ns
tDS
Input data (DI) Setup time
0.22
0.25
0.30
0.36
ns
tDH
Input data (DI) Hold time
0.00
ns
tCKQ1
Clock High to New Data Valid on DO (pass-through)
2.12
2.42
2.84
3.42
ns
tCKQ2
Clock High to New Data Valid on DO (pipelined)
0.69
0.79
0.93
1.12
ns
tRCKEF
RCLK High to Empty Flag Valid
1.53
1.74
2.05
2.46
ns
tWCKFF
WCLK High to Full Flag Valid
1.45
1.65
1.94
2.33
ns
tCKAF
Clock High to Almost Empty/Full Flag Valid
3.50
3.99
4.69
5.63
ns
tRSTFG
RESET_B Low to Empty/Full Flag valid
1.55
1.77
2.08
2.49
ns
tRSTAF
RESET_B Low to Almost-Empty/Full Flag Valid
3.43
3.91
4.59
5.52
ns
tRSTBQ
RESET_B Low to Data out Low on DO (pass-through)
0.82
0.94
1.10
1.32
ns
RESET_B Low to Data out Low on DO (pipelined)
0.82
0.94
1.10
1.32
ns
tREMRSTB
RESET_B Removal
0.30
0.34
0.40
0.48
ns
tRECRSTB
RESET_B Recovery
1.35
1.53
1.80
2.17
ns
tMPWRSTB
RESET_B Minimum Pulse Width
0.20
0.23
0.27
0.32
ns
tCYC
Clock Cycle time
1.94
2.20
2.59
3.11
ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
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