參數(shù)資料
型號： M7A3PE600-FPQG208I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PQFP208
封裝： 0.50 MM PITCH, GREEN, PLASTIC, QFP-208
文件頁數(shù)： 100/168頁
文件大?。?/td> 1335K
代理商： M7A3PE600-FPQG208I
ProASIC3E Flash Family FPGAs
A d v an c ed v0 . 5
2-25
Signal Descriptions for RAM512X18
RAM512X18 has slightly different behavior than the
RAM4K9, as it has dedicated read and write ports.
WW and RW
These signals enable the RAM to be configured in one of
the two allowable aspect ratios (Table 2-8).
WD and RD
These are the input and output data signals, and they
are 18 bits wide. When a 512x9 aspect ratio is used for
write, WD[17:9] are unused and must be grounded. If
this aspect ratio is used for read, RD[17:9] are undefined.
WADDR and RADDR
These are read and write addresses, and they are nine
bits wide. When the 256x18 aspect ratio is used for write
or read, WADDR[8] or RADDR[8] are unused and must be
grounded.
WCLK and RCLK
These signals are the write and read clocks, respectively.
They can be clocked on the rising edge or falling edge of
WCLK and RCLK.
WEN and REN
These
signals
are
the
write
and
read
enables,
respectively. They are both active low by default. These
signals can be configured as active high.
RESET
This active low signal resets the control logic and forces
the output hold state registers to zero when asserted. It
does not reset the contents of the memory array.
While the RESET signal is active, read and write
operations are disabled. As with any asynchronous reset
signal, care must be taken not to assert it too close to the
edges of active read and write clocks. Refer to the tables
beginning
with
for
the
specifications.
PIPE
This signal is used to specify pipelined read on the
output. A low on PIPE indicates a nonpipelined read, and
the data appears on the output in the same clock cycle. A
high indicates a pipelined read, and data appears on the
output in the next clock cycle.
Clocking
The dual-port SRAM blocks are only clocked on the rising
edge. SmartGen allows falling-edge triggered clocks by
adding inverters to the netlist, hence achieving dual-port
SRAM blocks that are clocked on either edge (rising or
falling). For dual-port SRAM, each port can be clocked on
either edge and/or by separate clocks by port.
ProASIC3E devices support inversion (bubble pushing)
throughout the FPGA architecture, including the clock
input to the SRAM modules. Inversions added to the
SRAM clock pin on the design schematic or in the HDL
code will be automatically accounted for during design
compile without incurring additional delay in the clock
path.
The two-port SRAM can be clocked on the rising edge or
falling edge of the WCLK and RCLK.
If negative-edge RAM and FIFO clocking is selected for
memory macros, clock edge inversion management
(bubble pushing) is automatically used within the
ProASIC3E development tools, without performance
penalty.
Modes of Operation
There are two read modes and one write mode:
Read
Nonpipelined
(synchronous—one
clock
edge): In the standard read mode, new data is
driven onto the RD bus in the same clock cycle
following RA and REN valid. The read address is
registered on the read port clock active edge and
data appears at RD after the RAM access time.
Setting PIPE to OFF enables this mode.
Read Pipelined (synchronous—two clock edges):
The pipelined mode incurs an additional clock
delay from the address to the data but enables
operation at a much higher frequency. The read
address is registered on the read port active clock
edge, and the read data is registered and appears
at RD after the second read clock edge. Setting
the PIPE to ON enables this mode.
Write (synchronous—one clock edge): On the
write clock active edge, the write data is written
into the SRAM at the write address when WEN is
high. The setup times of the write address, write
enables, and write data are minimal with respect
to the write clock. Write and read transfers are
described with timing requirements in the "DDR
RAM Initialization
Each SRAM block can be individually initialized on power-
up by means of the JTAG port using the UJTAG mechanism
ProASIC3/E SRAM/FIFO Blocks application note). The shift
register for a target block can be selected and loaded
with the proper bit configuration to enable serial
loading. The 4,608 bits of data can be loaded in a single
operation.
Table 2-8 Aspect Ratio Settings for WW[1:0]
WW[1:0]
RW[1:0]
DxW
01
512x9
10
256x18
00, 11
Reserved
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